ASIC Design Engineer - Pixel IP

About the position

Do you love crafting sophisticated solutions to highly complex challenges? As part of our Hardware Technologies group, you’ll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this highly transparent role, you will be at the center of the Pixel IP design effort to assemble and display breathtaking images and video. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.

Responsibilities

• Being responsible for the integration of large pixel-processing subsystems using SystemVerilog, connecting to high-performance on-chip networks using virtual memory addressing, adding Design-For-Test (DFT) logic, and managing clocks, resets, and power domains.
• Writing detailed micro-architectural specifications.
• Performing front-end implementation, including logic synthesis, clock & reset domain-crossing checks, static timing analysis, power analysis, logic equivalence checking.
• Working with Physical Design teams for physical floorplanning and timing closure.
• Collaborating with multi-functional teams to explore solutions that improve performance while minimizing power and area.
• Working closely with design verification and formal verification teams to debug and verify functionality and performance.

Requirements

• BS and a minimum of 3 years relevant industry experience.

Nice-to-haves

• Experience in IP/SoC front-end ASIC RTL digital logic design using Verilog and System Verilog.
• Extensive shown experience in ASIC implementation, especially logic synthesis, static timing analysis, logic equivalence checking, and working with physical design teams for floorplanning and timing closure.
• Deep experience with system design methodologies that contain multiple clock domains.
• Practiced in low-power design issues, tools, and methodologies including UPF power intent specification.
• Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
• Industry exposure to and knowledge of ASIC/FPGA design methodology including familiarity with relevant scripting languages (Python, Perl, TCL).
• Tight-knit collaboration skills with excellent written and verbal communication skills.
• Extensive experience working multi-functionally with integration, design, and verification teams to specify, design, and debug digital systems.