Circuits Design Engineer, Clock Design, University Graduate, PhD, Machine Learning

About the position

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Circuits Design Engineer, Clock Design you will collaborate with the architecture, logic design DFT, physical design, and circuits/technology teams to overcome the slowing of Moore's Law in advanced technology nodes and deliver cutting edge ASIC's and SoC's. You will drive block and full-chip level physical implementation of clock distribution and optimize related quality of results (i.e., power, timing, area). You will perform technical evaluations of EDA vendors, process nodes, and IPs and will provide recommendations. You will develop new and novel solutions and methodologies that co-optimize across the entire design space, then see these through from inception to maturity and tapeout.

Responsibilities

• Perform full chip clock planning. Create timing constraints and own the physical implementation of clock macros.
• Perform Spice simulations and run sign-off checks for the full-chip clock.
• Work with logic designers to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs for physical design closure.
• Perform technical evaluations of vendors, process nodes, and IPs and provide recommendations.
• Collaborate with teams across Google to develop ideas for high-impact clocking innovations for chip design projects.

Requirements

• PhD degree in Electrical Engineering or equivalent practical experience.
• Experience in clock architecture and designing high speed clock distribution circuits.
• Experience in Spice simulations, clock verification, and signoff.

Nice-to-haves

• Experience in ASIC physical design, physical design flows, and methodologies including synthesis, place and route, Static Timing Analysis (STA), formal verification, Change Data Capture (CDC), and power analysis.
• Experience in IP integration (e.g., Phase Lock Loops (PLLs), memories, and Analog IP) and analog routing.
• Experience in a scripting language (e.g., Python, Perl or TCL).
• Knowledge of Verilog/System Verilog.
• Familiarity with low power design techniques (e.g., multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS)/AVS, etc.).

Benefits

• 401k
• health_insurance
• dental_insurance
• vision_insurance
• life_insurance
• paid_holidays
• paid_volunteer_time
• tuition_reimbursement
• employee_stock_purchase_plan
• performance_bonus