About the position
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You are a highly motivated Principal Engagement Applications Engineer with over 15 years of hands-on experience in synthesis or place and route (P&R). You have a robust understanding of the most advanced CPU/GPU/NPU designs and are eager to work closely with R&D on driving product development and developing advanced HPC reference flow. Your technical expertise allows you to demonstrate differentiated PPA results on the most advanced IP cores to win benchmarking and deploy HPC methodologies to our worldwide key customers to accelerate business growth. You thrive in dynamic environments and possess excellent communication skills, including a strong command of English. Your background in EE/CS, coupled with your experience with EDA tools like DC, ICC2, and Fusion Compiler, makes you an ideal fit for this role.
Responsibilities
- Aggressively engaging in worldwide critical benchmarks and deployments to ensure the highest quality and performance of designs.
- Demonstrating differentiated PPA results on CPU/GPU/NPU designs to showcase our technology's superiority.
- Collaborating with R&D teams to drive product development and advanced HPC reference flow development for wide deployment.
- Deep dive debugging to address PPA bottlenecks and design challenges on the most advanced HPC designs and come with solution to solve it.
- Utilizing scripting languages such as Perl and Tcl for automation and optimization tasks.
- Staying updated with the latest advancements in ASIC design flow, VLSI, and CAD development to continually improve processes.
Requirements
- BS/MS in Electrical Engineering or Computer Science with 10+ years of relevant experience.
- Hands-on experience with synthesis, place and route (P&R) tools.
- Proficiency with EDA tools such as DC, ICC2, and Fusion Compiler.
- Strong understanding of timing constraint, timing analysis, power constraint, power analysis, routing congestion analysis.
- Knowledge of advanced placement, routing rules.
- Experience with scripting languages like Tcl, Python and Perl (Tcl is a must). Be able to proficiently use Tcl to analyze timing and design situation.
- Strong understanding of ASIC design flow, VLSI, and CAD development.
- Never give-up attitude and flexibility in supporting worldwide engagements.
Benefits
- Comprehensive health, wellness, and financial benefits.
- Annual bonus eligibility.
- Equity and other discretionary bonuses.
