About the position
As a GPU Design Integration Engineer, you will be responsible for creating GPU RTL by integrating various IPs following architectural parameters, physical constraints, DFT logic, and power intent. You will ensure implementation readiness with RTL lint, custom checks, and unit level synthesis. Your role will involve running logic equivalence checking between designs, developing innovative methods to improve the front-end design integration process, and collaborating effectively with Architecture, IP, DV, SOC, DFT, and IMPL teams spanning multiple sites. This position is part of the Silicon Technologies group, where you will help design and manufacture next-generation, high-performance, power-efficient GPUs that enable Apple products and services to handle tasks seamlessly.
Responsibilities
- RTL integration, partitioning, design analysis, qualification, packaging and delivery.
- Run logic equivalence checking between designs.
- Ensure implementation readiness with RTL lint, custom checks and unit level synthesis.
- Develop innovative methods to improve front-end design integration process.
- Understand and contribute to specifications for design units.
- Collaborate effectively with Architecture, IP, DV, SOC, DFT, IMPL teams spanning multiple sites.
Requirements
- BS + 3 years of relevant experience.
- Experience with Verilog/System Verilog.
- Experience with one of the following scripting languages: Perl/Ruby/Python.
Nice-to-haves
- Knowledge of PPA optimization techniques and implementation flows.
- Experience with scalable designs, DFT insertion, LEC, Lint and codeline management.
- Ability to debug and solve various design integration issues in a timely manner.
- Proficiency in logic design principles.
- Proficiency in programming techniques.
- Experience with RTL analysis and/or PPA optimization using Invio, LEC and Genus.
- Familiarity with GPU/CPU/SIMD Architecture and micro-architecture.
- Ability to solve complex problems across multiple technical domains.
- Ability to work well in a team and be productive under aggressive schedules.
