Physical Design Engineer

About the position

Seeking a hands-on Physical Design Engineer with 8–10 years of experience in pre-silicon validation, implementation, CAD, and block-level design. The ideal candidate will have strong technical expertise, excellent communication skills, and the ability to collaborate closely with customers and internal teams to ensure successful ASIC tapeouts.

Responsibilities

• Perform pre-layout Static Timing Analysis (STA) to validate feasibility and timing constraints.
• Handle chip/block-level floorplanning, pin assignments, and clock tree synthesis (CTS).
• Execute placement, timing optimization, routing, and physical design tasks.
• Conduct sign-off tasks, including RC extraction, IR drop analysis, and physical verification.
• Engage with customers, frontend, and integration teams to address design challenges and ensure smooth execution.
• Present technical findings and participate in customer meetings.

Requirements

• BSEE with 5+ years of experience (MSEE preferred).
• ASIC Physical Design experience, with 28nm/16nm tapeout experience.
• Proficiency in EDA tools (ICC2/Innovus) and scripting languages (Perl/Tcl/Python).
• Strong knowledge of ASIC frontend design and both flat and hierarchical layouts.
• Experience with power analysis (PrimePower/Redhawk), Static Timing Analysis (Primetime), and Physical Verification.
• Strong problem-solving skills and ability to resolve timing, library, and CAD tool-related issues.
• Excellent communication and customer-facing skills.