Principal Physical Design Engineer

About the position

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud, automotive, and carrier architectures, our innovative technology is enabling new possibilities. As a core member of Marvell's Central Physical Design team, you will provide backend design services to Marvell's SoC groups, working across a variety of complex designs that underpin data center, server, and networking applications. This team is dedicated to achieving high-performance and low-power goals for Marvell’s optical DSP and networking solutions, supporting multiple business models and targeting the forefront of data infrastructure.

Responsibilities

• Lead Chip-Level Physical Design: Oversee all aspects of chip-level Place and Route (PNR) activities, including floor planning, power grid design, clock tree synthesis, routing, and timing closure.
• Perform Detailed Analysis: Conduct comprehensive timing, power, and signal integrity signoff, ensuring designs meet stringent performance and reliability standards.
• Manage Physical Verification: Handle physical verification tasks such as DRC, LVS, and antenna checks to comply with advanced semiconductor process requirements.
• Collaborate Across Teams: Work closely with frontend, integration, and verification teams to ensure cohesive design implementation and successful project tapeouts.
• Develop Methodologies: Contribute to the development and refinement of physical design methodologies and flows, enhancing design efficiency and project alignment.
• Mentor and Lead: Provide technical guidance and mentorship to junior engineers, fostering a collaborative and innovative team environment.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
• 10+ years of hands-on experience in physical design and verification, with a proven track record in chip-level PNR and successful tapeouts of complex SoC designs.
• Expertise in hierarchical design strategies, deep sub-micron technologies (e.g., 7nm, 5nm), and familiarity with industry-standard physical design tools such as Cadence Innovus and Synopsys IC Compiler.
• Strong capabilities in timing analysis (e.g., Tempus, PrimeTime) and EM/IR-Drop/crosstalk analysis tools (e.g., Voltus, Celtic, PTSI).
• Proficiency in scripting languages (Makefile, Tcl, Perl) to automate and enhance design workflows.
• Detail-oriented, self-motivated, and effective communicator with a collaborative approach to team projects.

Benefits

• Flexible time off
• 401k
• Year-end shutdown
• Floating holidays
• Paid time off to volunteer