Radio Integration Engineer

About the position

Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a best-in-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture, and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. We encourage you to apply if you enjoy a fast-paced and challenging environment, collaborating with people across different functional areas, and growing during crisis times.

Responsibilities

• Work in a team developing Wireless SoCs with custom hardware accelerators and multiple ARM-based sub-systems.
• Integrate industry standard and custom hardware IP into SoCs.
• Collaborate with SoC architects and IP developers to develop SoCs that meet power, performance, and area goals.
• Define processes, methods, and tools for the design and implementation of large complex SoCs.
• Develop and maintain methodology and flow checks for designs.
• Interact with the verification team to ensure appropriate validation and coverage goals are met.
• Ensure security assumptions for the chip are accurately implemented within the blocks.
• Collaborate with multi-disciplinary groups to ensure designs are delivered on time and with high quality.
• Work with platform architects, system groups, and RFIC designers to develop digital modules within the RFIC.
• Design digital blocks for digitally intensive RF circuits like ADPLL, digital transmitters, and receivers.
• Develop signal processing intensive design for wireless communication SoCs.
• Write specifications and Microarchitecture definition.
• Perform IP integration, RTL logic design, and DV support.
• Run tools to ensure lint-free and CDC clean design.
• Conduct synthesis, timing constraints, equivalence check, and DFT insertion.
• Work with algorithm and software teams to ensure performance and power efficiency.
• Manage bus fabric, especially APB/AHB/AXI.
• Handle chip-to-chip interface, especially SPI, I2C, PCIe, and USB.
• Manage power with multiple power domains.

Requirements

• BS and 3+ years of relevant industry experience.

Nice-to-haves

• Detailed knowledge of the ASIC design flow, synthesis, static timing analysis, scripting, and netlist generation.
• Relevant design experience in SoC and/or radio/transceiver, PLL Controller.
• Experience with Digital Mixed Signal design.
• Extraordinary leadership skills and ability to encourage team members.
• Passion for owning and driving design schedules using well-defined metrics.
• Experience working in a high-energy multi-disciplined engineering environment.
• Strong multi-tasking and real-time crisis management skills.
• Ability to understand and extract action plans from sophisticated technical discussions.
• Excellent debugging skills and ability to drive resolution of critical problems.