Senior Engineer, Design Verification

Full-time - Senior

San Jose, CA

About the position

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities. The Design Verification team works on verifying and validating the design for our POCs, leveraging the latest methodology and tools for verification in the market. The candidate will work in a team that empowers its core members to use traditional techniques with innovative approaches to get the work done. We do not shy away from new ideas and methodologies as soon as they work for our purposes. As part of our research, one of our goals is to develop new techniques, and solutions and explore new concepts like AI applied to Verification.

Responsibilities

• Participate in verification strategy and methodology definitions
• Write Test plans, and participate on test plan definitions
• Responsible for the verification of modules/subsystems of design Modules
• Architect test benches, create test plans, implement test bench components in UVM
• Execute the verification per plan to the closure
• Work closely with architects and design engineers to define verification requirements, and to close functional and code coverage targets
• Work on constraints creation using SVA for functional Coverage
• Provide support in post silicon bring up and debug
• Complete other responsibilities as assigned

Requirements

• Bachelor in Electrical, Computer Science or related with 10+ years of experience or Master in Electrical, Computer Science, or related Science with 8+ years of Industry Experience or PhD in Electrical, Computer Science, or related Science with 5+ years of Industry Experience Preferred
• Experience in UVM
• Strong language skills including C++, SystemVerilog
• Experience in logic and SoC verification from planning to closure
• Good understanding of verification flows and tools
• Experience and/or knowledge of the emerging technologies (CXL, Computation in memory and storage, AI LLM accelerators, etc.) in server memory and storage systems
• Highly motivated with good verbal and written communication skills
• Creativity in problem-solving
• You’re inclusive, adapting your style to our people's situation and diverse global norms
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding
• You’re collaborative, building relationships, humbly offering support, and openly welcoming approaches
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

Benefits

• Medical/Dental/Vision/401k
• Charitable giving match
• 4+ weeks of paid time off a year, plus holidays and sick leave
• Stipend for fertility care or adoption
• Medical travel support
• Errand service
• On-demand apps and paid therapy sessions
• Onsite Café and gym, plus virtual classes
• Flexible environment