Senior Package Design Engineer

About the position

Astera Labs Inc. is a fabless semiconductor company who is a leader in developing purpose-built connectivity solutions that remove performance bottlenecks in compute-intensive workloads such as artificial intelligence and machine learning. To support our engineering operation, we are hiring a Senior Package Design Engineer with extensive experience of complex ASIC package design in Cadence APD, with SI/PI background a plus. As an Astera Labs Senior Package Design Engineer, you will be part of the packaging team that designs-in and supports Astera Labs’ portfolio of connectivity products in the world’s leading cloud service providers and server and networking OEMs. In this role, you are responsible to design the packages substrate independently from definition to package tape-out, by working on provided netlist and specification, through performance optimization, design for manufacturing, sign-off verification, etc. You will work in a cross-functional environment with SI/PI team, package program management, product engineering/test, hardware engineering, etc.

Responsibilities

• Design the packages substrate independently from definition to package tape-out.
• Work on provided netlist and specification, through performance optimization, design for manufacturing, sign-off verification.
• Collaborate with SI/PI team, package program management, product engineering/test, hardware engineering.
• Conduct DRC/DRV/LVS/DFM checks with given tools.
• Perform design review reporting, and Gerber and artwork releasing.
• Generate all required package design documentation.
• Perform feasibility studies such as fan-out, mockup design, layer & package size reduction.
• Drive new design flow development in APD with given new package types or technologies.
• Drive methodology and productivity improvements in package design by working with vendors or scripting.

Requirements

• BS/MS in Engineering Degree required (e.g., Electrical, Mechanical, Materials Science, Physics, etc.).
• Minimum of 5 years of experience with Cadence APD/SIP.
• Able to design and layout a FCBGA/FCCSP package from start to tape-out independently.
• Experience in large FCBGA/FCCSP package design in high speed SoC is highly desired.
• Familiar with BGA package substrate technologies and assembly process.
• Good understanding of BOM, stackups, high speed design rules and guidelines.
• Working knowledge of package reliability, SI/PI, etc.
• Excellent teamwork and collaboration skills.
• Strong communication skills to effectively work with cross-functional teams.

Nice-to-haves

• Multi-chip, interposer, 2.5D or heterogeneous package design experience.
• Proficiency in scripting languages for design and reporting automation.

Benefits

• Base salary range is USD 175,000 - USD 195,000.