Senior Staff Analog Mixed Signal IC Design Engineer

About the position

As an Analog IC Design Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.

Responsibilities

• Lead the high-speed and high performance SerDes development in advanced technology nodes, 5nm, 3nm, 2nm and beyond.
• Design IP that includes but is not limited to 224G/112G/56G PAM4; 32G PAM2; Die-to-Die High Speed Interconnect; System PLL IPs; General Analog Circuits.
• Participate in the SerDes architecture development with the DSP, Analog and Digital design teams.
• Provide instructions to the layout engineers.
• Work with the AE for the IP characterization and validation plan.
• Support IP Lab characterization and debugging.
• Provide product and customer support.

Requirements

• Master’s degree with 5+ years of experience and/or PhD in Electrical Engineering with 3+ years of experience in high speed analog mixed signal design in 7nm and below for TSMC process.
• PAM4, 56G, 112G and 224G SerDes Design experience highly desired.
• Demonstrable knowledge of high performance SerDes development.
• Demonstrable team player and works well in a collaborative environment.

Nice-to-haves

• Project leading and SOC support is preferred.
• Strives to make others better.

Benefits

• Flexible time off
• 401k
• Year-end shutdown
• Floating holidays
• Paid time off to volunteer