About the position
The High Speed IO design team delivers both proprietary and industry standard interfaces for IBM's POWER systems' and Z Mainframe's processors. With a current data rate up to 64Gbps and rising, verifying the functionality of the digital and analog components in an efficient manner is necessary. A verification engineer should be able to create test plans and testbenches to verify both logic and microcode provided by logic designers. They should communicate with the logic designer to create and review a test plan document, and then implement a testcase from the document. Testcases are written in either cycle sim or event sim, depending on the application. Simulations should be randomized appropriately and executed in large numbers through batch submissions. Coverage should be collected and analyzed with the logic designer. Some amount of logic debug ability is expected.
Responsibilities
- Create test plans and testbenches to verify logic and microcode.
- Communicate with logic designers to create and review test plan documents.
- Implement test cases from the test plan document.
- Write test cases in cycle sim or event sim.
- Randomize simulations and execute them in large numbers through batch submissions.
- Collect and analyze coverage with logic designers.
- Perform logic debugging as needed.
Requirements
- A minimum of 7+ years of verification experience in high-speed I/O or analog mixed-signal domain.
- Demonstrated experience in Verification.
- Proficiency in C++.
- Familiarity with C programming.
Nice-to-haves
- High-speed IO or Analog Mixed Signal Verification experience.
- Familiarity with IO SERDES design.
- Mixed Signal Analysis and design verification.
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