SoC UPF Design Engineer, Google Cloud

Google • Sunnyvale, CA

428d • $127,000 - $187,000

About The Position

As a SoC UPF Design Engineer at Google Cloud, you will be part of a diverse team dedicated to developing custom silicon solutions that enhance Google's direct-to-consumer products. This role involves working on SoC-level RTL design for data center accelerators, where you will own the top-level RTL, architecture, design, and implementation of global communication buses, as well as the integration of complex ASIC designs. You will collaborate with various ASIC development teams and contribute to defining methodologies that foster an efficient design environment for ASIC engineers.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 3 years of experience with RTL coding using Verilog/SystemVerilog.
• 2 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.

Nice To Haves

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
• Experience with low-power design techniques such as clock gating, power gating, and DVFS.
• Experience with SOC implementation standards, interfaces (i.e. AXI) and scripting languages (i.e. Tcl, Python or Perl).
• Experience in UPF for low-power design, including power intent specification, verification, and implementation.
• Experience with formal verification methods and design for testability (DFT) techniques.
• Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.

Responsibilities

• Contribute to the development and successful delivery of complex silicon systems.
• Design and implement RTL code for various digital blocks, including complex control logic and on-chip data paths.
• Develop and maintain Unified Power Format (UPF) specifications for power management of the design, including power domain definitions, power state transitions, and isolation strategies.
• Take ownership of power signoff using industry standard tools coordinating deliverables from block owners.
• Collaborate with verification and physical design engineers to ensure the functionality and power integrity of the design.
• Contribute to the development and improvement of design flows, tools and methodologies.

Benefits

• Health insurance
• 401(k) plan
• Paid holidays
• Flexible scheduling
• Professional development opportunities

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Web Search Portals, Libraries, Archives, and Other Information Services
• Education Level: Bachelor's degree