SOC Design Engineer - Physical design and Integration

About the position

We are looking for an SoC (System on Chip) Physical Design Engineer, ready to research, design, develop, and test lead Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry. This role is within Intel's highly-regarded Devices Development Group, headquartered in Portland, Oregon with additional sites in Penang, Malaysia, and Bangalore, India. Our bold purpose as a company is to 'create world-changing technology that enriches the lives of every person on earth' and this role is instrumental in furthering our mission to shape the future of technology.

Responsibilities

• SoC, clock design, and power delivery integration
• Driving performance optimization, including co-optimization work with process teams, to create best-in-class designs
• Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools
• Static timing analysis constraint understanding and generation, clock stamping, and timing closure
• Multiple Power Domain analysis using standard Power Formats UPF or CPF

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering with 5+ years of relevant experience, or master's degree (in same fields) with 3 years of relevant experience
• Relevant experience in backend design and/or integration in areas such as physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools
• Static timing analysis constraint understanding and generation, clock stamping, and timing closure
• Multiple Power Domain analysis using standard Power Formats UPF or CPF

Nice-to-haves

• 7+ years of experience in backend design and/or integration
• Product development and delivery on leading edge process nodes

Benefits

• Competitive pay
• Stock options
• Bonuses
• Health benefits
• Retirement plans
• Vacation