Sr. ASIC Ethernet Design Engineer

Cornelis Networks - Chesterbrook, PA

- Senior

Chesterbrook, PA

Professional, Scientific, and Technical Services

About the position

Cornelis Networks is hiring talented Sr. ASIC Design Engineers with deep experience in one or more of the key areas required to build the world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions. A good candidate will have 15+ years of ASIC design experience, with 10+ years of relevant experience in networking hardware design, proven expertise in 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec, and their application in high-speed data processing/networking.

Responsibilities

• End-to-end SoC/ASIC development.
• Front-end standard cell ASIC development including RTL development, Design Verification, synthesis, and post-silicon validation.
• Cross-functional collaboration and partnering with internal and external cross-functional teams, across all levels of the corporation.
• Define, implement, debug, and deliver system solutions around purpose-built ASICs.

Requirements

• 15+ years' post-college experience with silicon development.
• 15+ years' post-college experience in digital design with one or more HDL language (System Verilog, Verilog, VHDL).
• 10+ years of relevant experience in networking hardware design, proven expertise in 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec.
• 5+ years' post-college experience in one or more scripting language (TCL, Python, Perl).
• Understanding of Standard Cell ASIC development flow including digital design, IP integration, simulation and synthesis.
• B.S. degree in Computer Engineering, Computer Science, or Electrical Engineering.

Nice-to-haves

• M.S. degree in Computer Engineering, Computer Science, or Electrical Engineering.
• Track record of first-pass success in ASIC and Systems.
• Experience with multiple clock designs and asynchronous interfaces.