SiMa Technologies - San Jose, CA
posted 1 day ago
The MLA Design Verification (DV) team at SiMa is involved in the functional verification of Machine Learning Accelerator (MLA) and computer vision pipeline at block, sub-system and SoC level. Will also be involved in bringup and debug on emulator. As the MLA Design Verification Engineer, you will participate in MLA architecture, micro-architecture and feature discussions and reviews, define and develop MLA test bench components using UVM & SystemVerilog, develop DV reference models as needed in C or SystemVerilog, develop and execute a test plan, and perform verification execution of MLA and MLSoC functionality and performance measurements. You will lead code coverage reviews and closure, manage debug test and regression failures, as well as emulation failures, and work closely with the Architecture, MLSoC Hardware and MLA Software teams.
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