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SiMa Technologiesposted 29 days ago
$240,000 - $317,200/Yr
Full-time • Senior
San Jose, CA
Publishing Industries
Resume Match Score

About the position

The MLA Design Verification (DV) team at SiMa is involved in the functional verification of Machine Learning Accelerator (MLA) and computer vision pipeline at block, sub-system and SoC level. Will also be involved in bringup and debug on emulator. As the MLA Design Verification Engineer, you will participate in MLA architecture, micro-architecture and feature discussions and reviews, define and develop MLA test bench components using UVM & SystemVerilog, develop DV reference models as needed in C or SystemVerilog, develop and execute a test plan, and perform verification execution of MLA and MLSoC functionality and performance measurements. You will lead code coverage reviews and closure, manage debug test and regression failures, as well as emulation failures, and work closely with the Architecture, MLSoC Hardware and MLA Software teams.

Responsibilities

  • Participate in MLA architecture, micro-architecture and feature discussions and reviews
  • Define and develop MLA test bench components using UVM & SystemVerilog
  • Develop DV reference models as needed in C or SystemVerilog
  • Develop and execute a test plan
  • Verification execution of MLA and MLSoC functionality and performance measurements
  • Lead Code coverage reviews and closure
  • SystemVerilog Assertion functional coverage development and closure
  • Manage debug test and regression failures, as well as emulation failures
  • Work closely with the Architecture, MLSoC Hardware and MLA Software teams

Requirements

  • BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 15+ years of experience in functional verification of pipe-line based design preferably MLAs, DSPs, CPUs or GPUs
  • Very good experience of UVM and SystemVerilog based verification methodology is a must
  • Proficiency in C/C++ programming is a plus
  • Working experience on emulation is a plus
  • Skill set for silicon debug on the lab/board set-up
  • Good debug and problem solving skill

Benefits

  • Annual salary range from $240,000 - $317,200
  • Equal opportunity employer

Job Keywords

Hard Skills
  • Code Coverage
  • Computer Science
  • Machine Learning
  • SystemVerilog
  • Test Planning
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  • hVYB8y0z chbzOdTrR
  • jvBSp9 ZbHJDU8o GWsy97UnaBzcP
  • QI3zAxB pAcMiLnH7Zgwz
  • wsXrbejk14v KEayC74SRPrl
Soft Skills
  • 1Pmz98lN BDO6HyX9
  • hqUzIdax hUGyi7wn
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