System Level Test Engineer, PhD, University Graduate, Google Cloud

About the position

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a System Level Test Engineer, you'll help to integrate System on Chip (SoC) technologies into High Performance Computing Products. You'll develop and automate system-level manufacturing test of ASIC's and SoC's to validate performance and screen out bad devices. In this role, you will participate in all aspects of System level Test and Product Engineering activities. You will work with ASIC Architecture, Design, and Pre-silicon SoC Verification teams to define test methodologies and implement manufacturing solutions. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Develop System Level Test (SLT) solutions for custom ASIC's and SoC's by specifying hardware and integration requirements, driving vendor interactions, developing software frameworks and test modules, and integrating test cases from silicon validation and system software and test teams.
• Partner with data center server and accelerator design teams to realize practical test solutions leveraging system design and test elements.
• Partner with hardware and software teams to evaluate functional device yield and performance across various operating conditions, characterize hardware/software interaction, and develop effective production screens to reduce Defective Parts per Million (DPPM).
• Integrate test software and hardware solutions with robotic chip handlers, drive bring-up of fully integrated solutions in internal and partner NPI labs, transfer all collaterals needed for High Volume Manufacturing (HVM) at Offshore Assembly and Test (OSAT) facilities, and provide ongoing HVM support.

Requirements

• PhD in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
• Experience with hardware testing of systems based on custom ASIC's or SoC products.
• Experience with Linux/Unix, Python programming, or basic TCP/IP network configuration.

Nice-to-haves

• Experience with hardware and/or semiconductor testing.
• Experience implementing secure ASIC/SoC manufacturing solutions (e.g., provisioning, e-fuse programming, and/or lifecycle management).
• Proficiency in C#, .NET Framework, C/C++, and/or Perl.
• Knowledge of ASIC/SoC Boot process and/or CPU performance testing.

Benefits

• Bonus
• Equity
• Health benefits