Applications Engineering, Sr Engineer

$109,000 - $163,000/Yr

Synopsys - Sunnyvale, CA

Full-time - Mid Level

Sunnyvale, CA

Publishing Industries

About the position

The primary focus of this Verification Applications Engineer position at Synopsys is to support the sale and adoption of the Synopsys Verification solution. As a Verification Applications Engineer, you will be instrumental in driving the effort to enable the verification methodology and solution for customers utilizing Synopsys Verification tools. This role requires a deep understanding of RTL simulation and System Verilog/UVM testbench development, along with excellent debugging skills. You will engage directly with customers to assist in deploying verification tools and methodologies, resolving technical issues, and providing technical training to ensure successful implementation and usage of the tools. In this role, you will be expected to have experience with both Block Level and SOC Level simulation verification. Proficiency in System Verilog/UVM, Verilog, and VHDL is essential. You should also possess knowledge of Constrained Random Verification and Code/Functional/Assertions (SVA) Coverage closure. Excellent debugging skills in designs and within the System Verilog/UVM environment are crucial, and familiarity with debugging tools such as Verdi and nWave will be beneficial. Critical thinking and problem-solving skills are necessary to navigate complex technical challenges, and strong verbal and written communication skills are required to effectively present information and interface with customers. At Synopsys, we are at the forefront of innovations that transform the way we work and play, including advancements in self-driving cars, artificial intelligence, cloud computing, 5G, and the Internet of Things. We are committed to powering these breakthroughs with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Inclusion and diversity are core values at Synopsys, and we consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Responsibilities

• Support the sale and adoption of the Synopsys Verification solution.
• Drive the effort to enable verification methodology and solution for customers using Synopsys Verification tools.
• Assist customers with the deployment of verification tools and methodologies.
• Resolve technical issues related to verification tools.
• Provide technical training to customers on verification methodologies and tools.

Requirements

• Experience with Block Level and SOC Level simulation verification.
• Proficiency in System Verilog/UVM, Verilog, and VHDL.
• Knowledge of Constrained Random Verification and Code/Functional/Assertions (SVA) Coverage closure.
• Excellent debugging skills on designs and within the System Verilog/UVM environment.
• Experience with debugging tools such as Verdi and nWave.
• Strong critical thinking and problem-solving skills.
• Good verbal and written presentation/communication skills.
• Strong organizational skills and good customer interface skills.

Benefits

• Comprehensive health benefits
• Wellness benefits
• Financial benefits
• Annual bonus eligibility
• Equity and discretionary bonuses