ASIC Design Engineer - Memory Cache Controller

$138,900 - $256,500/Yr

Apple - Santa Clara, CA

Full-time - Mid Level

Santa Clara, CA

Computer and Electronic Product Manufacturing

About the position

Apple is building the world's fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth, and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy. You will participate in Cache micro architecture development from specifications found from architecture guidelines and model analysis. This involves exploring architecture trade-offs in system performance, area, and power consumption along with the performance analysis team. You will also be responsible for developing and debugging RTL design of different sections of the cache. Collaboration with the physical design team will be essential to close timing of the same, ensuring that the designs meet the required specifications and performance metrics.

Responsibilities

• Participate in Cache micro architecture development from specifications found from architecture guidelines and model analysis.
• Explore architecture trade-offs in system performance, area, and power consumption along with the performance analysis team.
• Develop and debug RTL design of different sections of the cache.
• Work with the physical design team to close timing of the cache design.

Requirements

• Development of memory systems.
• Experience in RTL/micro-architecture definition.
• Experience in PPA (performance/power/area) analysis.
• Knowledge of dedicated coherent memory system or interconnect architectures.
• Strong cache design background including good understanding of different memory organizations and tradeoffs.
• Knowledge of dedicated memory subsystem and DRAM controller.
• Hands-on experience with multi-processor cache coherence protocols.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain educational expenses including tuition
• Discretionary bonuses or commission payments
• Relocation assistance
• Participation in Apple's discretionary employee stock programs
• Eligibility for discretionary restricted stock unit awards
• Ability to purchase Apple stock at a discount through Employee Stock Purchase Plan