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Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. This role is within our ASIC team, specifically as part of the Design for Test group. As a member of Acacia's ASIC team, you will set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC and SCAN at chip and/or block level and set up pattern generation flow for Scan/ATPG & MBIST/Repair/Fuse. You will work with seasoned DFT engineers to implement and verify DFT. You will also interact with RTL/PD/STA/ATE, collaborating with them for a successful tape out.
