ASIC Design for Test Technical Leader

Valtix - San Jose, CA

Full-time - Senior

San Jose, CA

Publishing Industries

About the position

This is an onsite role and will require working out of the Milpitas/San Jose office location. The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Responsibilities

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• Craft solutions and debug with minimal mentorship.

Requirements

• Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 10 years of experience.
• Knowledge of the latest innovative trends in DFT, test and silicon engineering.
• Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime.
• Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design.
• Prior experience with Gate level simulation, debugging with VCS and other simulators.
• Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687.
• Prior experience with Scripting skills: Tcl, Python/Perl.

Nice-to-haves

• Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification.
• DFT CAD development - Test Architecture, Methodology and Infrastructure.
• Background in Test Static Timing Analysis.
• Past experience with Post silicon validation using DFT patterns.

Benefits

• Quality medical, dental and vision insurance.
• 401(k) plan with a Cisco matching contribution.
• Short and long-term disability coverage.
• Basic life insurance.
• Numerous wellbeing offerings.
• Paid holidays including one floating holiday and a day off for birthday.
• Vacation time off policy with flexible limits.
• Sick time off policy with 80 hours provided on hire date.
• Paid time away to deal with critical or emergency issues.
• Additional paid time to volunteer and give back to the community.