ASIC Design Verification Engineer

Chelsea Search - Minneapolis, MN

Full-time - Senior

Minneapolis, MN

Administrative and Support Services

About the position

The Senior ASIC Design Verification Engineer will take ownership of the full-chip development process, from architecture definition to production release. This role requires a hands-on engineer with extensive experience in designing complex digital blocks and a strong understanding of the complete ASIC/SOC design flow. The ideal candidate will also have experience in radiation-hardened design, analog/mixed-signal design, and EDA, as well as std-cell library development.

Responsibilities

• Reviewing and editing target specifications for completeness and feasibility.
• Developing architectures and specifications for complex design blocks and SOCs.
• Implementing complex digital designs using reusable RTL methods (Verilog, VHDL, SystemVerilog).
• Designing complex computational architectures and algorithms, such as multi-rate/DSP and -P design.
• Utilizing modern verification methods, including directed/constrained-random stimuli, assertions, TLM, and UVM.
• Collaboratively creating comprehensive verification plans and coverage metrics.
• Applying multi-supply-domain and UPF methods.
• Constraining and synthesizing digital designs to target cell libraries.
• Conducting static timing, power, and SI analyses of complex digital designs.
• Supporting place & route efforts, including P/G and floorplanning, timing and physical constraints, gated CTS, MCMM setups, back-annotation, timing closure, and equivalence checking.
• Planning, implementing, and analyzing designs for DFT, test hooks, and scan/ATPG/JTAG/BIST, and supporting production test with ATPG patterns and timeset definitions.

Requirements

• Bachelor's/Master's in Electronic Engineering/Computer Science or equivalent.
• 10+ years of direct industry experience with ASIC and/or SoC design.
• Strong background in RTL based digital IC design using Verilog/SystemVerilog.
• Proven track record of first-pass successes.
• Ability to work well in a diverse team environment.
• Willingness to mentor less senior engineers.

Nice-to-haves

• Experience with radiation-hardened design.
• Experience with analog/mixed-signal design and EDA.
• Experience with std-cell library development.

Benefits

• Full-time employment with direct-hire status.
• Health insurance coverage.
• 401k retirement savings plan.
• Paid holidays and vacation time.