ASIC Engineering Manager, Design Verification

Meta - Sunnyvale, CA

Full-time - Manager

Sunnyvale, CA

5,001-10,000 employees

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About the position

The ASIC Engineering Manager for Design Verification at Meta is responsible for leading a team focused on the verification of ASIC designs within a System on Chip (SoC) environment. This role involves driving verification planning, execution, and the development of innovative methodologies to ensure first-pass success in ASIC development. The manager will collaborate with various cross-functional teams and contribute to the overall silicon strategy aligned with corporate objectives.

Responsibilities

• Manage an ASIC design verification team responsible for various processing blocks in a SOC.
• Drive verification planning and execution, innovative verification methodology development, functional and code coverage closure.
• Participate in silicon architecture and micro-architecture development, interfacing with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams.
• Partner with internal and external cross-functional teams across all levels of the corporation.
• Contribute to and drive the development of the overall silicon strategy aligned to the corporation's Long Range Plan objectives.
• Collaborate with IP development teams and support soft and hard IP identification, selection, and licensing.
• Identify candidates, hire, schedule, support, and train a team of ASIC engineers to develop products on time and on budget.
• Analyze and review SOWs from vendors and supporting documentation to meet internal customer needs.
• Support engineering teams to define, debug, implement, and deliver total solutions around purpose-built ASICs.
• Define, implement, and maintain key performance indicators (KPI) for areas of responsibility.
• Partner with technical program management and supply chain team members to manage external development partners, suppliers, and vendors.

Requirements

• B.S. or M.S. degree in Computer Engineering or Electrical Engineering, or equivalent practical experience.
• 10+ years experience managing ASIC/SoC design verification teams at the Director or Manager level.
• Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium Simulator, Verdi, JasperGold or VC Formal.
• Track record of first-pass success in ASIC Development.
• Experience working across multiple projects and adjusting priorities in partnership with stakeholders.
• Experience managing and delivering UVM constrained random test benches.
• Experience with interpreting functional specs and creating comprehensive test plans.

Nice-to-haves

• Hands-on experience with complex subsystems like memory/LPDDR/HBM, cache, PCIE or Network on chip and with performance verification.
• Knowledge of video coding standards, signal processing algorithms, neural networks and machine learning concepts, and/or other neural network development frameworks.
• Experience in formal verification techniques and methodologies.
• Experience with managing and delivering Formal Verification sign-off for complex designs.

Benefits

• Health insurance coverage
• Dental insurance coverage
• 401k retirement savings plan
• Paid holidays
• Flexible scheduling
• Professional development opportunities