ASIC/FPGA Validation, Sr Engineer

Synopsys • Sunnyvale, CA

330d • $103,000 - $155,000 • Onsite

About The Position

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You are a highly skilled and motivated ASIC Digital Design Engineer with a passion for innovation and technology. With a strong background in RTL and FPGA design, you possess the expertise necessary to take on complex challenges and deliver cutting-edge solutions. You have a keen eye for detail and thrive in a collaborative environment where you can leverage your extensive knowledge of Verilog, SystemVerilog, and Universal Verification Methodology (UVM) to verify and validate designs. Your proficiency in Linux, C, C++, and scripting languages such as Perl, Python, and TCL sets you apart as a versatile and resourceful engineer. Moreover, your familiarity with protocols like AXI, USB, and PCIe, coupled with your experience in data structures and algorithms, equips you to handle intricate projects efficiently. You excel in utilizing lab equipment such as protocol analyzers, oscilloscopes, and logic analyzers to perform hardware validation tasks and debug IPs. Your educational background, with a minimum of a B.S. in Electrical Engineering, Computer Science, Computer Engineering, or a related field, along with 1 to 5 years of relevant experience, demonstrates your commitment to excellence and continuous learning.

Requirements

• Experience in FPGA design and development.
• Proficiency in Verilog/SystemVerilog for RTL design and verification.
• Experience with Linux, C, C++, and scripting languages such as Perl, Python, and TCL (highly desired).
• Knowledge of protocols including AXI, USB, and PCIe (highly desired).
• Strong understanding of data structures and algorithms (highly desired).
• Hands-on experience with lab equipment such as protocol analyzers, oscilloscopes, and logic analyzers.

Responsibilities

• Designing, implementing, and achieving timing closure for RTL and FPGA using Xilinx & Synopsys development tools.
• Verifying designs in simulation using Verilog, SystemVerilog, and UVM.
• Creating comprehensive user documentation.
• Developing and executing test plans for USB IP.
• Bringing up and validating designs in the lab and generating detailed test reports.
• Performing hardware validation tasks and debugging IPs.
• Reading, understanding, and modifying software drivers and scripts as needed.

Benefits

• Comprehensive health, wellness, and financial benefits.
• Annual bonus eligibility.
• Equity and other discretionary bonuses.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Publishing Industries
• Education Level: Bachelor's degree