ASIC Hardware and Firmware Co-Verification Engineer

AMD - Ontario, CA

Full-time

Ontario, CA

Computer and Electronic Product Manufacturing

About the position

The ASIC Hardware and Firmware Co-Verification Engineering role at AMD focuses on the co-verification of hardware and firmware for embedded micro-processor subsystems within the Security IP Team. This position involves developing and verifying embedded firmware for secure boot and hardware acceleration services, as well as contributing to firmware development initiatives. The role requires strong analytical skills and the ability to work collaboratively in a diverse environment, aiming to enhance the performance of various SoC functions such as cryptography and data compression.

Responsibilities

• Development and verification of embedded firmware for SOC secure boot and embedded microprocessor driven hardware acceleration services for cryptography, decompression and large scale DMA functions
• Hardware/Firmware co-verification in UVM System Verilog and C-DPI structured testbench
• Hardware/Firmware co-verification in FPGA hardware prototype platform
• Develop and maintain subsystem verification architecture, testbench, test methodology for Embedded CPU and subcomponent IPs with AXI/AHB busses and HW accelerators
• Participate in subsystem specification, influence IP micro-architecture development
• Develop and verify abstracted performance model
• Create abstracted FW and HW performance models
• Develop critical target code to collect IP performance key parameters
• Explore subsystem architecture performance trade-off for FW and HW optimization
• Develop and execute subsystem and block level test plans
• Develop FW/HW co-verification methodology
• Develop UVC and System Response models
• Develop and debug UVM and C-DPI test cases with integrated FW
• Improve verification metrics
• Further develop subsystem and block level testbenches using UVM randomized test methodology and C-DPI directed test methodology
• Develop and maintain subsystem level integration scripts
• Develop and maintain subsystem testbench build and test run scripts
• Drive to verification metrics closure
• Interface with SoC integration and SoC DV teams
• Define and develop IP level DV API to support SoC level DV effort
• Develop and maintain IP build and delivery infrastructure to support SoC level integration of SMU IPs
• Support SoC level IP emulation, silicon bring-up and debugging effort

Requirements

• ASIC FW and HW design and verification experience
• Proficient in C, C++, Assembly, Verilog, System Verilog, and several scripting languages (Make, Perl, Python, etc.)
• Excellent knowledge about UVM methodology and C-DPI methodology
• Excellent knowledge about standard bus/interface protocols (i.e. AXI, AHB, AMBA)
• Excellent experience with firmware design on commercial microprocessors
• Excellent experience with microprocessor tool chain, compiler, assembler, debugger
• Excellent experience with ASIC verification tools, simulation, linting, power aware simulation, etc.

Benefits

• AMD benefits at a glance