ASIC Physical Design Engineer

Synopsys • Boxborough, MA

373d • $139,000 - $209,000 • Onsite

About The Position

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You are a highly motivated individual with a passion for technological innovation and continuous improvement. You thrive in a fast-paced environment and are eager to contribute to cutting-edge projects. You possess a solid engineering understanding of the underlying concepts of IC design and have strong knowledge of the full design cycle from RTL to GDSII, including the development of timing constraints. Your expertise in the implementation flows and methodologies for deep sub-micron designs is unparalleled. You have experience in high-performance digital design, CAD, high-speed design, low-power design, and high-speed clock design and distribution. You have a proven track record of contributing to project tape-outs and are proficient in timing closure and signal integrity. Your software and scripting skills (Perl, Tcl, Python) are top-notch, and you have knowledge of CAD automation methods. You are a team player who can interface with the larger product team to understand design constraints, deliverable formats, and customer requirements. With at least 10+ years of layout and physical design experience, you have hands-on experience with the design of complex ASSP and COT designs and are familiar with Synopsys tools, flows, and methodologies.

Requirements

• Solid engineering understanding of IC design concepts
• Strong knowledge of the full design cycle from RTL to GDSII
• Expertise in implementation flows and methodologies for deep sub-micron designs
• Experience in high-performance digital design, CAD, high-speed design, low-power design, and high-speed clock design and distribution
• Proven experience with project tape-outs and timing closure
• Proficiency in software and scripting skills (Perl, Tcl, Python)
• Knowledge of Synopsys tools, flows, and methodologies

Responsibilities

• High speed Die to Die PHY Floor planning, power planning, placement, and optimization
• Analog building block layout construction and PPA optimization
• Clock tree building and optimization
• Routing and optimization
• Timing constraints closure, synthesis, and formal verification
• Extraction, IR drop analysis, EM analysis, and signal integrity
• Physical verification and flow development for advanced technology nodes
• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle
• Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals
• Timing, physical and electrical verification, and driving the signoff closure for the partitions
• Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution

Benefits

• Comprehensive health, wellness, and financial benefits
• Annual bonus eligibility
• Equity and other discretionary bonuses
• Competitive total rewards package

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Industry: Publishing Industries