ASIC RTL Design Engineer, Machine Learning Accelerators

$127,000 - $187,000/Yr

Google - Madison, WI

Full-time - Mid Level

Madison, WI

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About the position

As an ASIC RTL Design Engineer focused on Machine Learning Accelerators at Google, you will be part of a diverse team dedicated to developing custom silicon solutions that enhance Google's direct-to-consumer products. This role involves contributing to the design and implementation of cutting-edge ASICs that accelerate Machine Learning computations in Google's data centers, ensuring high performance and efficiency in hardware experiences.

Responsibilities

• Create and review ASIC/SoC subsystem design architecture and microarchitecture specifications independently and collaboratively.
• Develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines.
• Work with Design Validation (DV) teams to create test plans for, verify, and debug design RTL.
• Collaborate with physical design teams to ensure design meets physical requirements and achieves timing closure.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 2 years of experience in Digital design using SystemVerilog RTL.

Nice-to-haves

• Master's degree or PhD in Electrical Engineering or Computer Science.
• 4 years of experience in digital/ASIC design using SystemVerilog or RTL.
• Experience in one or more successful ASIC products from concept to silicon.
• Experience interacting with software, system hardware, and other cross-functional teams.
• Experience defining SoC IP interfaces and methodologies.
• Understanding in computer architecture/memory subsystem architecture.

Benefits

• Health insurance
• Dental insurance
• Vision insurance
• 401(k) plan with matching contributions
• Paid holidays
• Paid time off
• Employee stock purchase plan
• Tuition reimbursement
• Professional development opportunities