ASIC RTL Design Engineer, Machine Learning Accelerators
Google•Sunnyvale, CA
488d•$127,000 - $187,000
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About The Position
The ASIC RTL Design Engineer for Machine Learning Accelerators at Google will be responsible for developing Application-Specific Integrated Circuits (ASICs) that enhance machine learning computations in Google's data centers. This role involves defining micro-architecture specifications, implementing Register-Transfer Level (RTL) designs, and collaborating with software teams to ensure effective solutions. The engineer will contribute to the innovation of hardware experiences that deliver exceptional performance and efficiency for Google's products.
