ASIC/SoC Design Verification Engineer

$110,000 - $300,000/Yr

Intellipro - Fremont, CA

Full-time - Mid Level

Fremont, CA

Professional, Scientific, and Technical Services

About the position

The ASIC/SoC Design Verification Engineer will play a critical role in the verification of System on Chip (SoC) designs, collaborating closely with design engineers and architects to define, document, and implement detailed test plans. This position requires building and maintaining the infrastructure and environment necessary for automated verification of SoC architecture, function, and performance. The engineer will be responsible for developing reusable testbenches, constrained-random and directed test cases, as well as verification-related behavioral modules for both block and system levels. Additionally, the engineer will develop regression strategies, methodologies, and tools, while defining and measuring function coverage to ensure thorough verification before design releases and tape-out. Debugging and identifying root causes of simulation failures in collaboration with design engineers is also a key responsibility, along with supporting test engineers during post-silicon validation. In this role, the engineer will also have the opportunity to mentor and coach team members and junior engineers, driving verification efficiency and fostering a collaborative team environment. The ideal candidate will possess a strong background in verification methodologies and tools, with a focus on ensuring high-quality design outputs. This position is suited for individuals who thrive in a startup environment and can work both independently and as part of a team, providing technical leadership to fellow engineers.

Responsibilities

• Collaborate with design engineers and architects to define, document, and implement detailed test plans for SoC design verification.
• Build and maintain infrastructure/environment for automation verification of SoC architecture, function, and performance.
• Develop reusable testbench, constrained-random/directed test cases, and verification associated behavioral modules for both block levels and system levels.
• Develop regression strategy, methodology, and tools/scripts; define and measure function coverage.
• Close verification holes for design releases and tape-out; work with design engineers to debug and identify root causes of simulation failure.
• Support test engineers for post-silicon validation.
• Mentor and coach team members and junior engineers; drive verification efficiency.

Requirements

• MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science, or related degree.
• In-depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware/software co-verification methodology.
• Extensive experience in building verification infrastructure, test planning, coverage closure, testbench, and test case development for function/performance verification.
• Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C, and industry mainstream ISAs assembly coding.
• Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM, or DSP core.
• Experience in verifying designs at both RTL level and post-P&R gate level.
• Ability to work in a startup environment, independently and as a team player, providing technical leadership.

Nice-to-haves

• Working knowledge of AI/ML Computing, GPU, ISP architectures, and accelerators.
• Experience in verifying mixed-signal design and interface of digital and analog.
• Experience of design verification for high-speed IO such as PCIE and DDR.

Benefits

• Comprehensive benefits package subject to eligibility.