ASIC Verification Engineer

About the position

The ASIC Verification Engineer primary job function is Pre-Silicon Design Verification Machine Learning IP and SOC designs using industry standard verification methodologies.

Responsibilities

• Pre-Silicon Design verification of next generation Machine Learning IPs and SoCs, blocks and/or chip top-level.
• Collaborate with other team members to define a verification methodology and a test plan.
• Develop IP level verification environments including stimulus generators, monitors, scoreboards, and coverage collectors.
• Build self-checking test benches for SoC blocks and chip top-level verification.
• Develop verification plan for IP and SOC features.
• Generate directed and random test cases, write regression scripts, and report code and functional coverage.
• Do a first level debug for root cause classification (TB, HW, or SW issue), and work with design team to validate fixes or workarounds.
• Run Gate level simulations, and replicate Silicon/FPGA bugs in the test bench environment.
• Develop and grow verification infrastructure to improve verification productivity and regression management.
• Contribute to identifying and adopting best engineering practices with cross functional teams.

Requirements

• BS/MS in Electrical Engineering or related degree or certification required.
• 2+ years of experience in System Verilog or UVM/OVM based verification.
• Good skills in verification methodology, test planning and test bench architecture.
• Very good experience with System Verilog and advanced verification techniques: constrained random verification, code/functional/assertion coverage.
• Experience in integrating Verification IPs, and HW/SW Co-Simulation is a plus.
• Knowledge of ARM based SoC architecture and system busses (AHB, AXI, APB) is strongly desired.
• Knowledge of standard SoC interfaces (SPI, I2C, etc.) and high-speed IO protocols (PCIe, USB, DDR) is a plus.
• Programming skills in C++, Python, and shell scripting are strongly desired.
• Good debugging skills, and well experienced with VCS/Verdi or similar toolsets.