Avionics FPGA Design and Verification Chief Principal Engineer

$177,650 - $257,600/Yr

Boeing - Hazelwood, MO

Full-time - Principal

Hazelwood, MO

Transportation Equipment Manufacturing

About the position

The Avionics FPGA Design and Verification Chief Principal Engineer at Boeing is responsible for leading a team of engineers in the technical development of FPGA solutions for various avionics products. This role involves overseeing the design, verification, and certification processes for FPGA systems used in critical applications such as Vehicle Management Systems and Guidance and Control Units. The position requires collaboration with cross-functional teams to ensure that designs meet customer requirements and are delivered on schedule.

Responsibilities

• Lead FPGA designs, including multi-FPGA programs and teams with design and verification engineers, and manage team execution to meet program milestones
• Collaborate with customers, system engineers, and hardware engineers to drive requirements capture and architect digital logic functions to meet mission/customer needs
• Explore trade-space of potential FPGA technologies and determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance
• Implement FPGA with latest design practices and tools from block-level microarchitecture and through HDL coding
• Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensure the design is completed on schedule
• Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation
• Create self-checking and reusable test benches from scratch, applying Object Oriented Programming concepts such as Inheritance and Polymorphism, and leverage UVM to create drivers, monitors, predictors, and scoreboards
• Drive FPGA-based prototyping and validation depending on program and system requirements and complexity
• Validate design through hardware integration test with special test equipment, test-beds, and higher-level systems as needed
• Train and mentor less senior engineers across the department and help build effective project teams

Requirements

• Bachelor of Science degree from an accredited course of study in engineering, engineering technology, chemistry, physics, mathematics, data science, or computer science
• 10 or more years of professional experience with Hardware-based integration and test of ASIC/FPGA designs
• 10 or more years of educational and/or work experience working with digital ASIC/FPGA design and verification

Nice-to-haves

• Experience with hardware emulators
• Experience leading FPGA design and/or verification teams, including tracking and reporting progress to stakeholders
• Proficiency with hardware verification languages: System Verilog, System Verilog Assertions
• Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.
• Ability to create test plans and self-checking and reusable testbenches from scratch
• Experience developing Functional Coverage Models and Closing Code Coverage
• Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)
• Proficient in scripting languages: Make, Perl, Python, etc.
• Familiarity with space-based design techniques and radiation mitigation
• Experience with MIL-STD-882E
• Experience with DO-254

Benefits

• Health insurance
• Flexible spending accounts
• Health savings accounts
• Retirement savings plans
• Life and disability insurance programs
• Paid and unpaid time away from work