Cellular ASIC Design Integration Engineer

$131,500 - $243,300/Yr

Apple - San Diego, CA

Full-time - Mid Level

San Diego, CA

10,001+ employees

Computer and Electronic Product Manufacturing

About the position

As a Cellular ASIC Design Integration Engineer at Apple, you will play a pivotal role in the design and development of cellular subsystems that are integral to Apple’s products and services. This position is not just about technical expertise; it requires a passion for crafting elegant solutions to complex challenges and a keen eye for detail. You will be part of a dynamic team that is at the forefront of chip design, ensuring that Apple’s offerings can seamlessly handle the tasks that make them beloved by millions. This high visibility and mission-critical role will provide you with excellent exposure to multiple VLSI design technologies and flows, and it will require you to build close working relationships with various functional teams across the organization. Your responsibilities will include contributing to the definition, architecture, design, and development of cellular subsystems. You will perform all aspects of the front-end design flow, which encompasses integration, connectivity, releases, design checks, verification reviews, memory built-in self-test (MBIST), design for test (DFT), synthesis, and timing constraints. Additionally, you will conduct power analysis, evaluate different design trade-offs, and drive power improvements. Developing design methodologies for scalable designs and providing pre/post-silicon debug support will also be key aspects of your role. This position is ideal for someone who thrives in a collaborative environment and is eager to make a significant impact on the future of technology at Apple.

Responsibilities

• Contribute to definition, architecture, design, and development of cellular subsystems.
• Perform all aspects of front-end design flow including integration, connectivity, releases, design checks, verification reviews, MBIST, DFT, synthesis, and timing constraints.
• Conduct power analysis and evaluate different design trade-offs to drive power improvements.
• Develop design methodologies for scalable designs.
• Provide pre/post-silicon debug support.

Requirements

• BS degree in Electrical Engineering or related field and 3+ years of relevant industry experience.
• Thorough knowledge of the ASIC design flow, front-end design, low power design, and design verification.
• Strong knowledge of RTL design and HDL languages (Verilog, System Verilog, etc.).
• Experience with front-end tools (CDC, RDC, LINT, Formal, LP Checks, LEC, PTPX).
• Strong analytical skills to make design trade-offs for performance, area, and power.
• Experience in driving power improvements based on power analysis tools/flows.
• Familiarity with UPF flow for defining power intent of chips with multiple power domains.
• Experience with version control tools and handoff of design releases.
• Strong scripting skills to automate tasks and build scalable design flows.
• Understanding of synthesis and static timing analysis (STA) constraints.

Nice-to-haves

• Familiarity with DFT, MBIST, synthesis, STA, and backend related methodology and tools.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain educational expenses, including tuition
• Discretionary bonuses or commission payments
• Relocation assistance
• Participation in Apple's discretionary employee stock programs
• Opportunity to purchase Apple stock at a discount through the Employee Stock Purchase Plan.