CPU Design Architect / Principal Digital Design Engineer

Baidu - Sunnyvale, CA

Full-time

Sunnyvale, CA

Computer and Electronic Product Manufacturing

About the position

The position involves designing a cost-effective controller for a cellular modem, focusing on high performance, low power consumption, and compact area. The role requires collaboration with international teams and encompasses CPU development, design integration, and research into new CPU architecture technologies.

Responsibilities

• Perform CPU development and design integration for MIPS CPU subsystem.
• Explore latest technologies and conduct fundamental research on new directions in CPU architecture.
• Contribute ideas for advanced CPU performance features.
• Analyze workloads in detail to identify performance bottlenecks and opportunities.
• Adopt a data-driven approach to trade-offs in CPU design.
• Derive architecture and micro-architecture for the design/model implementation team.
• Bring innovative ideas to successful silicon.

Requirements

• Master's Degree in Electrical Engineering, Computer Science, or Computer Engineering.
• At least 5 years of CPU related Architect/RTL/Verification/Implementation design experience.
• Knowledge and practical experience with common RISC CPU architecture.
• Familiarity with chip digital design flow, including RTL integration, simulation, and STA.
• Understanding of high performance techniques and trade-offs in CPU microarchitecture.
• Ability to problem solve and validate own ideas.

Nice-to-haves

• PhD in Electrical Engineering, Computer Science, or Computer Engineering is a PLUS.
• 8+ years of CPU related Architect/RTL/Verification/Implementation design experience.
• Strong knowledge of CPU architecture and micro-architecture.
• Familiarity with Symmetric Multi-processing (SMP) and Snoop-based multi-processor architecture.
• Familiarity with synthesis, power analysis, and post-silicon debugging.
• Cross-site working experience is a PLUS.
• Common knowledge in modeling/DV/OS is a PLUS.
• Experience with Foundry, Post-Silicon, FPGA, DVT, SLT debug is a PLUS.