CPU Design Timing Engineer

Apple - Austin, TX

Full-time - Entry Level

Austin, TX

Computer and Electronic Product Manufacturing

About the position

As the CPU Design Timing Engineer at Apple, you will play a crucial role in ensuring the timing closure of our cutting-edge CPU projects. This position requires a deep understanding of timing analysis and the ability to collaborate effectively with various teams, including the implementation and RTL teams. You will be responsible for developing and modifying timing flows, conducting timing analysis, and driving timing closure to meet project deadlines. Your work will directly impact the performance and efficiency of our CPU designs, making it essential to have a strong foundation in both theoretical and practical aspects of CPU microarchitecture and timing methodologies. In this role, you will work closely with the CAD team to create and refine the timing flow used throughout the project. This includes scripting to enhance analysis flows and improve engineering efficiency. You will also collaborate extensively with CPU micro-architects and implementation engineers to ensure that timing closure is achieved effectively. Your contributions will be vital in shaping the next generation of Apple products, as you help to deliver innovative solutions that redefine industry standards. The ideal candidate will bring a passion for technology and a commitment to excellence, as well as a collaborative spirit that fosters teamwork and innovation. At Apple, we value creativity and dedication, and we are looking for individuals who are eager to contribute to our mission of delivering extraordinary products and experiences to our customers.

Responsibilities

• Develop and modify timing flows for CPU projects.
• Conduct timing analysis and ensure timing closure for CPU designs.
• Collaborate with the CAD team to improve analysis flows and engineer efficiency through scripting.
• Work closely with CPU micro-architects and implementation engineers to drive timing closure.

Requirements

• Minimum BS in Electrical Engineering or related field.
• Understanding of solid-state devices and circuit design.
• Knowledge of CPU microarchitecture and common critical loops for timing.
• Familiarity with low power microarchitecture and implementation techniques for CPUs.
• Basic experience with static timing tools and flows.
• Physical design knowledge, particularly aspects impacting timing such as cross talk, noise, and OCV.
• Good understanding of physical design tools and methodologies, including physically aware synthesis and place & route tools.