CPU Physical Design and Integration Engineer

$143,100 - $264,200/Yr

Apple - Santa Clara, CA

Full-time - Mid Level

Santa Clara, CA

Computer and Electronic Product Manufacturing

About the position

As a CPU Physical Design and Integration Engineer at Apple, you will play a pivotal role in the physical design, integration, and verification of high-performance, low-power processor development. This position is highly visible and places you at the center of a processor design effort, interfacing with various disciplines to ensure the successful delivery of functional products to millions of customers. Your contributions will directly impact the speed and efficiency of product launches, making your role critical in the overall design cycle. In this role, you will be responsible for full chip floorplanning, area optimizations, block partitioning, and pin placements. You will own the chip-level place and route (PnR) processes, construct the final CPU layout database, and ensure thorough verification (PDV). Additionally, you will develop and validate the Power Grid, including conducting routability analysis, and drive custom layout integration. Collaboration with the implementation and CAD teams throughout the chip design cycle will be essential to achieve signoff closure for tapeout. You will also work closely with the SOC team to meet IP technical and delivery requirements, participate in establishing CAD and physical design methodologies, and contribute to flow development for chip integration and analysis. Scripting to automate tasks and improve debug efficiency will also be a key part of your responsibilities.

Responsibilities

• Participate in the physical design, integration, and verification of high-performance, low-power processors.
• Conduct full chip floorplan, area optimizations, block partitioning, and pin placements.
• Own chip level place and route (PnR) and final CPU layout database construction and verification (PDV).
• Develop and validate Power Grid, including routability analysis.
• Drive custom layout integration and collaborate with implementation/CAD teams during the chip design cycle.
• Ensure signoff closure for tapeout and work with SOC team to meet IP technical and delivery requirements.
• Establish CAD and physical design methodologies and participate in flow development for chip integration and analysis.
• Script to automate tasks and improve debug efficiency.

Requirements

• BS degree in Electrical Engineering or related field.
• 3+ years of relevant industry experience in physical design, integration, and verification (PDV) on large processor and/or SoC designs.
• Knowledge of industrial standards and practices in physical design, including floorplanning, partitioning, budgeting, place and route, and physical verification.
• Experience using synthesis and place-route tools.
• Knowledge of low power design, physical construction, integration, PDV, DRC/LVS verification.
• Solid understanding of scripting languages, such as Perl/Tcl.
• Solid understanding of CMOS circuit design; layout design background is a plus.
• Working knowledge of extraction, STA, EMIR methodology, and tools.
• Ability to work well in a team, be an excellent problem solver, and be self-motivated.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain educational expenses, including tuition
• Discretionary bonuses or commission payments
• Relocation assistance
• Participation in Apple's discretionary employee stock programs
• Opportunity to purchase Apple stock at a discount through the Employee Stock Purchase Plan