Design Engineering Architect

Cadence Design Systems - San Jose, CA

Full-time - Senior

San Jose, CA

Professional, Scientific, and Technical Services

About the position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Cadence Silicon Solution Group (SSG) develops industry-leading IPs that enable our customers in a variety of markets - from the endpoint to the edge to the cloud and AI for SoC and chiplets. At Cadence, we're helping set the standard on IP products that get integrated into SoCs and chiplets powering the world's Data Centers, Automobiles, Cloud, wired/Wireless, and AI-enabled systems. Cadence SSG IP business is growing fast. We're expanding our San Jose team and looking for smart, energetic, collaborative, and creative people to join this exciting growth opportunity and help us lead the industry with Cadence IP products for silicon solutions. The Design Engineering Architect role in physical design within SSG is a technical and project leadership position. This role is responsible for working with IP design teams and silicon solution architects to develop new physical aware IP architectures. The architect will collaborate with leading foundries such as TSMC, Samsung, and Intel to achieve the best Performance/Power/Area (PPA) for Cadence IPs. Additionally, the architect will guide Cadence's worldwide physical design teams to follow the best design practices and methodologies. The position requires over 15 years of experience in design tools, foundry technologies, and proven leadership in collaborating and coordinating cross-functional teams and external companies to develop industry-leading IPs for advanced technology nodes at world-leading semiconductor foundries. Cross-functional project management experience with strong communication and interpersonal skills are essential. A thorough understanding and experience with the full physical design flows, including RTL Synthesis, floorplan, P&R, high-performance clock-tree synthesis, static Timing analysis and closure, DFT, and Low power design techniques, is required. Deep knowledge and experience with Cadence tools/flows (Genus, Innovus, Voltus, Tempus, Modus, Conformal-LP, Pegasus) is also necessary. Good knowledge of high-performance interface PHYs and controllers is highly desirable.

Responsibilities

• Work with IP design teams and silicon solution architects to develop new physical aware IP architectures.
• Collaborate with leading foundries such as TSMC, Samsung, and Intel to achieve optimal Performance/Power/Area (PPA) for Cadence IPs.
• Guide Cadence worldwide physical design teams to follow best design practices and methodologies.
• Manage cross-functional projects and coordinate with external companies to develop industry-leading IPs for advanced technology nodes.
• Utilize deep knowledge of Cadence tools/flows (Genus, Innovus, Voltus, Tempus, Modus, Conformal-LP, Pegasus) in design processes.
• Ensure thorough understanding and execution of full physical design flows including RTL Synthesis, floorplan, P&R, and static Timing analysis.

Requirements

• 15+ years of experience in design tools and foundry technologies.
• Proven leadership in collaborating and coordinating cross-functional teams and external companies.
• Experience in developing industry-leading IPs for advanced technology nodes at leading semiconductor foundries.
• Strong communication and interpersonal skills.
• Thorough understanding of full physical design flows including RTL Synthesis, floorplan, P&R, high-performance clock-tree synthesis, static Timing analysis and closure, DFT, and Low power design techniques.
• Deep knowledge and experience with Cadence tools/flows (Genus, Innovus, Voltus, Tempus, Modus, Conformal-LP, Pegasus).

Nice-to-haves

• Good knowledge of high-performance interface PHYs and controllers.