Synopsys - Austin, TX

posted 2 months ago

Full-time - Mid Level
Austin, TX
Publishing Industries

About the position

At Synopsys, we are at the forefront of innovations that are transforming the way we work and play, including advancements in self-driving cars, artificial intelligence, the cloud, 5G, and the Internet of Things. Our System Solutions Group is dedicated to shaping dependable systems that prioritize safety, security, reliability, and low power consumption. We collaborate closely with customers and industry partners to understand their needs and identify the technical requirements necessary for their success. Our passion for methodologies and automation drives us to make our customers' jobs easier as they develop their products. We are currently seeking a Design Layout Engineer specializing in Advanced Packaging. This role is critical as it involves working on the rapidly growing area of advanced packaging and multi-die design implementation. Utilizing the industry's most advanced silicon design tools, you will provide comprehensive solutions that encompass architecture and design partitioning, floorplanning, routing, and simulation of advanced packaging designs. You will engage with various cross-functional teams to integrate multiple designs into a cohesive system, gaining expertise in chip-to-chip interfaces such as HBM3/4, UCIe, 3DIO, and high-speed IPs like PCIe and memory interfaces such as DDR5 and LPDDR. In this position, you will drive the progress of cutting-edge multi-die designs that power the most innovative GPUs and CPUs in the industry. You will also contribute to the latest technological advancements in multi-die packaging techniques such as CoWoS, InFO, and 3DIC. This role offers an exciting opportunity to be at the heart of technological innovation in the semiconductor industry.

Responsibilities

  • Provide end-to-end solutions for advanced packaging designs, including architecture and design partitioning, floorplan, route, and simulation.
  • Engage with cross-functional teams to integrate multiple designs into a system.
  • Gain expertise in chip-to-chip interfaces such as HBM3/4, UCIe, 3DIO, and high-speed IPs like PCIe and memory interfaces like DDR5 and LPDDR.
  • Drive the progress of multi-die designs for innovative GPUs and CPUs.
  • Contribute to advancements in multi-die packaging techniques such as CoWoS, InFO, and 3DIC.

Requirements

  • BSEE/MSEE in Electrical and/or Computer Engineering.
  • At least 5 years of experience in physical design and SOC development.
  • Knowledge of Synopsys EDA tools like 3DIC Compiler, IC Compiler II, or Fusion Compiler.
  • Experience in backend implementation, simulation, and sign-off, including EMIR, ESD, STA, and thermal simulation.
  • Understanding of CAD flows, tools, and design methodology development for backend tools.

Nice-to-haves

  • 2.5/3D packaging experience and knowledge of CoWoS, InFO, RDL.
  • Experience with multiple tapeouts in advanced nodes such as 14-/10-/7-nm.
  • Custom layout experience for analog and RF.
  • Experience in digital place and route, including floorplanning and signal/power/ground design using leading APR tools.
  • Experience with chip-level thermal and EMIR analysis using Redhawk and generated CPM models.
  • Direct customer interaction experience.
  • Ability to lead backend and physical design development through GDS and collaborate with partners and foundries for design reviews and tape-outs.

Benefits

  • Comprehensive health benefits
  • Wellness programs
  • Financial benefits including equity and discretionary bonuses
  • Competitive total rewards package
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