Design Verification Engineer (#91887)

$151,091 - $155,000/Yr

Rival Limited - Santa Clara, CA

Full-time

Santa Clara, CA

Clothing, Clothing Accessories, Shoe, and Jewelry Retailers

About the position

The position involves silicon design verification for high-performance coherent fabric, focusing on ensuring functional correctness through collaboration with various engineering teams. The role requires developing tests and implementing verification techniques to achieve tape-out quality, while also managing project schedules and enhancing verification workflows.

Responsibilities

• Collaborate with architect, RTL designer, and other verification teams to define functional correctness.
• Develop tests using assembly, C/C++, SystemVerilog, or test vectors based on predefined plans.
• Create coverage monitors to assess comprehensive feature coverage and reach tape-out quality.
• Implement SystemVerilog or C-based checkers for end-to-end design verification.
• Write assertions and employ formal verification techniques to assess design correctness.
• Develop testbench from scratch and create directed/constrained random test cases.
• Investigate and triage test failures from RTL simulations, tracking and documenting identified issues.
• Manage project schedules and support cross-functional engineering efforts.
• Assist in enhancing verification workflows, automation scripts, and regression testing procedures.

Requirements

• Master's or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field.
• Prior coursework or project experience in cache coherence protocol and network-on-chip design.
• Experience in debugging and triaging simulation test failures via waveform and logs.
• Proficiency in object-oriented programming, C, C++, System Verilog, Python, Perl, and algorithms.
• Knowledge of parallel computer architecture.

Benefits

• Salary range of $151,091 - $155,000 per year.