Design Verification Engineer - FPGA/ASIC

As a Design Verification Engineer at Viasat, you will be part of a dynamic team focused on developing cutting-edge communications technology. This role involves full-cycle RTL verification for FPGA and ASIC designs, including planning, test environment development, and quality assurance through coverage metrics analysis. You will work in a collaborative environment utilizing modern tools and methodologies to ensure high-quality outputs and timely project delivery.