Digital Design Engineer, Micro-Architect, Principal

$180,000 - $300,000/Yr

D-matrix Corporation - Santa Clara, CA

Full-time - Principal

Santa Clara, CA

51-100 employees

Professional, Scientific, and Technical Services

About the position

d-Matrix is seeking a Principal Digital Design Engineer specializing in Micro-Architecture to join our innovative team in Santa Clara, CA. This role is pivotal in the design and micro-architecture of AI sub-system modules, including SIMD and Hardware Execution Engines. The successful candidate will be responsible for defining and implementing a Custom Instruction Set Architecture (ISA) and collaborating with System Architects to develop efficient C-Kernels utilizing this Custom ISA. The position requires ownership of the design process, including documentation, execution, and delivery of fully verified, high-performance, area, and power-efficient Register Transfer Level (RTL) designs that meet specified design targets. In this role, you will engage in the design of micro-architecture and RTL, as well as synthesis, logic, and timing verification using cutting-edge CAD tools and semiconductor process technologies. You will also be tasked with designing and implementing logic functions that facilitate efficient testing and debugging, and you will participate in silicon bring-up and validation for the blocks you own. This position is essential for advancing our digital in-memory compute (DIMC) engine, which is at the forefront of AI compute technology, aiming to minimize data movements and enhance performance for Large Language Models. As part of a dynamic team, you will contribute to the development of next-generation AI solutions, leveraging your expertise in micro-architecture and digital design to drive innovation and efficiency in our products. d-Matrix is committed to delivering cutting-edge technology and is on track to launch its first commercial product in 2024, making this an exciting time to join our team.

Responsibilities

• Design and micro-architect AI sub-system modules including SIMD and Hardware Execution Engines.
• Define and implement Custom Instruction Set Architecture (ISA).
• Collaborate with System Architects to develop efficient C-Kernels utilizing the Custom ISA.
• Own the design, documentation, execution, and delivery of fully verified, high-performance, area, and power-efficient RTL.
• Engage in the design of micro-architecture and RTL, synthesis, logic, and timing verification using leading-edge CAD tools.
• Design and implement logic functions for efficient test and debug processes.
• Participate in silicon bring-up and validation for owned blocks.

Requirements

• Bachelor's degree in Electrical Engineering or a related field, plus a Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Minimum of 5 years of meaningful work experience in micro-architecture and RTL development (Verilog/System Verilog).
• Experience focused on high-speed Processor and sub-system design, Digital Signal Processing blocks.
• Exposure to Mixed-signal designs, Computer Architecture, and Arithmetic is required.
• Good understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.
• Strong interpersonal skills and ability to work effectively in a team.

Nice-to-haves

• Experience with RISC V, Tensilica, ARM, or MIPS processors.
• Advanced knowledge in Computer Architecture and Arithmetic.