Amentum - Odon, IN

posted about 2 months ago

Full-time
Odon, IN
Professional, Scientific, and Technical Services

About the position

Amentum is seeking a Digital Twin & Hardware Emulation Project Lead to support the emulation of microelectronics and microelectronics systems at the Naval Surface Warfare Center, Crane Division. This role involves establishing a digital engineering (DE) and emulation capability at NSWC Crane, providing oversight to an external contractor in developing a digital twin, and ensuring that the NSWC Crane team is kept updated on all developments. The position is structured as a typical 40-hour work week, with very rare overtime requirements. Additionally, a 9/80 work schedule is available, allowing for every other Friday off. The Project Lead will be responsible for achieving defined goals of the DE capability through various means, including using DE/emulation to evaluate higher-level abstraction design simulations to assist in architectural evaluations and choices at the beginning of ASIC design. The role also involves helping to transition existing board-level systems facing obsolescence into the DE environment to design drop-in replacements. Furthermore, the Project Lead will import existing ASIC technical data packages into the DE/emulation environment for software bring-up and mission scenario simulations. Utilizing subject matter expertise, the Project Lead will assist in developing a strategy for investing in DE/emulation hardware, software, and workforce over the next five years, as well as creating a roadmap for the next two and five years to achieve these strategic goals. This position requires a strong background in microelectronics emulation and familiarity with various design and simulation tools, as well as the ability to think strategically and plan initiatives involving hardware, software, and workforce.

Responsibilities

  • Support the establishment of a digital engineering (DE)/emulation capability at NSWC Crane.
  • Provide oversight to an external contractor on developing a digital twin.
  • Keep the NSWC Crane team updated on all developments.
  • Use DE/emulation to evaluate higher level of abstraction design simulations to assist in architectural evaluations/choices at the beginning of ASIC design.
  • Help transition existing board level systems facing obsolescence into the DE environment to design drop-in replacements.
  • Import existing ASIC technical data package into DE/emulation environment for software bring up and mission scenario simulations.
  • Assist in the development of a strategy for investing in DE/emulation hardware, software, and workforce over the next five years.
  • Create a roadmap for the next 2 years to achieve the DE strategy.
  • Create a roadmap for the next 5 years to achieve the DE strategy.

Requirements

  • Bachelor's degree in electrical engineering or related Physical Science.
  • 15+ years of relevant experience.
  • Experience with Microelectronics emulation with at least one piece of current EDA vendor emulation equipment (Cadence Palladium preferred, Siemens Veloce, Synopsys ZeBu).
  • Familiarity with microelectronics board/system level design/simulation.
  • Ability to read and understand schematics and block diagrams.
  • Experience with BOMs and Gerber files.
  • Familiarity with microelectronics component level design/simulation.
  • Experience with RTL design and logic simulations.
  • Knowledge of PDKs and SPICE models.
  • Experience with TLM/system C modeling (Synopsys Platform Architect experience is a bonus).
  • Familiarity with emulation projects.
  • Experience modeling/simulating microelectronics for a project in a DE environment.
  • Experience modeling/simulating a microelectronics-based system for a project in a DE environment.
  • Strategic high-level thinking.
  • Ability/experience with planning an initiative involving hardware/software/workforce.
  • Must be able to obtain and maintain a US Government Secret Clearance.

Nice-to-haves

  • Active Secret Clearance.
  • Graduate degree.
  • Combination of Digital ASIC/FPGA design/verification AND higher level DE/emulation experience and strategic high-level planning.
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