Amentum - Odon, IN

posted about 2 months ago

Full-time
Odon, IN
Professional, Scientific, and Technical Services

About the position

Amentum is seeking a Digital Twin & Hardware Emulation Project Lead to support the emulation of microelectronics and microelectronics systems at the Naval Surface Warfare Center, Crane Division. This role is critical in establishing a digital engineering (DE) and emulation capability at NSWC Crane, where the Project Lead will provide oversight to an external contractor tasked with developing a digital twin. The Project Lead will ensure that the NSWC Crane team is kept updated on all developments related to this initiative. The position typically involves a 40-hour work week, with very rare overtime requirements. Additionally, a 9/80 work schedule is available, allowing for every other Friday off, which provides flexibility and work-life balance. The Project Lead will be responsible for achieving defined goals of the DE capability through various means, including using DE/emulation to evaluate higher levels of abstraction design simulations that assist in architectural evaluations and choices at the beginning of ASIC design. The role also involves helping to transition existing board-level systems facing obsolescence into the DE environment to design drop-in replacements. Furthermore, the Project Lead will import existing ASIC technical data packages into the DE/emulation environment for software bring-up and mission scenario simulations. Utilizing subject matter expertise, the Project Lead will assist in developing a comprehensive strategy for investing in DE/emulation hardware, software, and workforce over the next five years, as well as creating roadmaps for the next two and five years to achieve these strategic goals. This position requires a blend of technical knowledge, strategic planning, and leadership skills to drive the success of the digital engineering initiatives at NSWC Crane.

Responsibilities

  • Support the establishment of a digital engineering (DE)/emulation capability at NSWC Crane.
  • Provide oversight to an external contractor on developing a digital twin.
  • Keep the NSWC Crane team updated on all developments related to the digital twin project.
  • Use DE/emulation to evaluate higher level of abstraction design simulations for architectural evaluations at the beginning of ASIC design.
  • Assist in transitioning existing board level systems facing obsolescence into the DE environment for designing drop-in replacements.
  • Import existing ASIC technical data packages into the DE/emulation environment for software bring-up and mission scenario simulations.
  • Develop a strategy for investing in DE/emulation hardware, software, and workforce over the next five years.
  • Create a roadmap for the next 2 years to achieve the DE strategy.
  • Create a roadmap for the next 5 years to achieve the DE strategy.

Requirements

  • Bachelor's degree in electrical engineering or related Physical Science.
  • 15+ years of relevant experience in microelectronics emulation.
  • Experience with at least one piece of current EDA vendor emulation equipment (Cadence Palladium preferred, Siemens Veloce, Synopsys ZeBu).
  • Familiarity with microelectronics board/system level design/simulation.
  • Ability to read and interpret schematics and block diagrams.
  • Experience with BOMs and Gerber files.
  • Familiarity with microelectronics component level design/simulation.
  • Experience with RTL design and logic simulations.
  • Knowledge of PDKs and SPICE models.
  • Experience with TLM/system C modeling (Synopsys Platform Architect experience is a bonus).
  • Familiarity with emulation projects.
  • Experience modeling/simulating microelectronics for a project in a DE environment.
  • Experience modeling/simulating a microelectronics-based system for a project in a DE environment.
  • Strategic high-level thinking and planning experience involving hardware/software/workforce.
  • Ability to obtain and maintain a US Government Secret Clearance.

Nice-to-haves

  • Active Secret Clearance.
  • Graduate degree in a relevant field.
  • Combination of Digital ASIC/FPGA design/verification and higher level DE/emulation experience.
  • Experience in strategic high-level planning.
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