Digital Verification Lead - Perm - San Francisco/Silicon Valley OR Pittsburgh

Elevate Digital

Full-time - Mid Level

Professional, Scientific, and Technical Services

About the position

The Digital Verification Lead will oversee the digital verification strategy for the company's first-generation product, ensuring high-quality SoC development. This role involves collaboration with engineering teams and external service providers to create specifications, test plans, and manage verification processes. The position offers a unique opportunity to influence product development and internal processes as the company transitions from initial product stages to market release.

Responsibilities

• Develop SoC specifications in collaboration with the design team that describe the functionality of various chip components, including the expected inputs, outputs, and state machines.
• Write digital SoC verification plans and scope digital verification development tasks, including the development of functional coverage groups.
• Develop a reusable test bench and portable test components that can be used to verify both full systems and system components.
• Manage external 3rd-party digital verification service providers to ensure deadlines are met and project plans are adhered to.
• Act as liaison between external service providers and the engineering teams to ensure requirements are met, troubleshoot as needed, and facilitate regular meetings.
• Collect, collate, analyze, and present coverage reports. Work closely with digital designers to determine a strategy to close any coverage gaps.
• Support running gate-level simulations as part of design signoff.
• Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions.
• Assist in developing internal processes and frameworks to improve code quality, coverage, and correctness.

Requirements

• 4+ years of Digital SoC Verification project management experience with specific experience managing small external teams of verification engineers and/or vendors.
• Experience writing and maintaining System Verilog test benches and test components.
• Bachelor's degree in Engineering or a related field is required; Master's degree or PhD is a plus.
• Minimum 5+ years of experience in design verification.
• Experience writing custom and reusable verification infrastructure (drivers, monitors, agents, and models).
• Well-versed in coverage-driven, constrained random verification, including coverage analysis and coverage closure.
• Ability to analyze performance and correctness regressions to determine their root cause.
• Experience with script development for work automation, preferably experience with Python.

Nice-to-haves

• Knowledge of computer architecture, processor design and implementation, hardware and software engineering, and software development toolchains is a plus.
• Knowledge of UVM/OVM or equivalent portable verification methodologies, as well as IEEE-1801 (UPF) simulation flows is a plus.

Benefits

• Competitive compensation package
• 401K match
• Company-paid benefits
• Equity program
• Paid parental leave
• Flexibility
• Personal and professional development opportunities