Electronic-Photonic Process Design Kit (PDK) Development Engineer

MIT Lincoln Laboratory - Lexington, MA

Full-time - Mid Level

Lexington, MA

Professional, Scientific, and Technical Services

About the position

The Electronic-Photonic Process Design Kit (PDK) Development Engineer at MIT Lincoln Laboratory is responsible for developing and maintaining process design kits for various fabrication processes, particularly for photonic integrated circuits (PICs). This role involves working within a multi-disciplinary team to implement and mature PDKs, utilizing Cadence tools to create technology files, parameterized cell libraries, and documentation for layout changes. The engineer will also collaborate on mask layout and ensure the continuous evolution of cutting-edge technologies.

Responsibilities

• Implement, apply, maintain, and mature process design kits (PDKs) for silicon-based and compound-semiconductor fabrication processes.
• Create technology files and code parameterized cell libraries in the Cadence environment.
• Document code and methodology updates, as well as layout changes.
• Collaborate with team members on mask layout from basic cell creation to final tapeout.
• Create DRC and LVS decks as technologies mature.

Requirements

• Five or more years' experience with developing technology files and design environments in Cadence or similar tools.
• Five or more years' experience with coding parameterized layout cells, ideally in the Cadence Virtuoso (SKILL) environment.
• Experience working on multiple inter-related PDKs and layouts.
• Ability to work independently with minimal supervision and collaboratively as part of a dynamic, multi-disciplinary team.
• Excellent organization and communication skills both within and across disciplinary boundaries.

Nice-to-haves

• Bachelor's or Master's degree in electrical engineering, computer science, materials science, physics, chemistry, or a related field.
• Experience with photonic integrated circuit PDK development or mask layout.
• Experience with mask floor-planning, creating custom layout blocks, and mask aggregation.
• Experience with LVS beyond traditional CMOS technologies.
• Knowledge of the Advanced-Node version of Cadence, programming in Perl, TCL, or Python, RF layout design experience, or experience with Cadence CurvyCore.

Benefits

• Comprehensive health, dental, and vision plans
• MIT-funded pension
• Matching 401K
• Paid leave (including vacation, sick, parental, military, etc.)
• Tuition reimbursement and continuing education programs
• Mentorship programs
• A range of work-life balance options