Engineer, DRAM Design Rule

Micron Technology - Boise, ID

Full-time - Senior

Boise, ID

Computer and Electronic Product Manufacturing

About the position

As a DRAM Design Rule Engineer at Micron Technology, you will be responsible for creating and maintaining design rules for the development of advanced DRAM nodes. This role involves collaboration across various teams to ensure the optimization of performance, power, area, and cost for Micron's DRAM products, while also addressing process issues and ensuring compliance with established design rules.

Responsibilities

• Collaborate with Process Integration, Process Development, Design, Product Engineering, CAD and other areas to develop and maintain design rules for advanced DRAM nodes.
• Define mbits for DRAM array.
• Assist with reticle making from concept to fab including design, layout, scribe and test structure, reticle manufacturing specs and pre-tapeout checks.
• Work with Design Enablement Team to evaluate test structures to provide data for next generation devices and to quantify process margin on current devices.
• Define sub-milestones for the project within the layout schedule and work with various teams to achieve targets and timelines.
• Pro-actively identify and address process issues and process window vs. die size issues stemming from specific database layout or layout techniques.
• Partner with Design, Product Engineering, Process Integration, Business Units and Quality groups to optimize PPAC (Performance, Power, Area, Cost) for all Micron DRAM products.
• Assure that the right DRC's (Design Rule Checks) are in place, and ensure appropriate reaction to deviation from established design rules.
• Strategically partner with multiple teams to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design.
• Summarize sophisticated problems, derive and explain actions taken to address them.
• Drive effective multi-functional communication on issue resolution, and support across node Design Rule alignment.
• Maintain and implement meaningful communication between Process Integration, Product Engineering, Design, and Advanced Mask teams.
• Improve timely documentation of R&D activities regarding design rule improvements for transfer to parts still in design.

Requirements

• BS/MS/PhD in Electrical Engineering, Microelectronics, Physics or related field.
• Senior level (5+ years) experience in the semiconductor industry in areas such as Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development, or Unit Process Development.
• Solid grasp and exposure to design & layout with the ability to do minor layout and work with Pcells.
• Experience with Test Structure Design and characterization.
• Success in resolving sophisticated issues.
• Ability to think and communicate clearly in urgent and stressful situations.
• Deep understanding of the DRAM process flow and the function and purpose of major DRAM components, such as Sense Amp, Word-line driver, and Anti-Fuse.
• Exposure and familiarity with CAD group interactions, data post-processing, and the process of transferring data from the database to the reticle.

Benefits

• Choice of medical, dental and vision plans.
• Income protection programs for illness or injury.
• Paid family leave.
• Robust paid time-off program.
• Paid holidays.