Fab11x EMIB/FOVEROS Technology Product Integration Development Engineer

Intel - Albuquerque, NM

Full-time - Entry Level

Albuquerque, NM

Computer and Electronic Product Manufacturing

About the position

Intel's Advanced Packaging (AP) technologies extend and drive Moore's Law as the company aspires to a trillion transistors in a package by 2030. Intel has led the industry in disaggregated advanced packaging for a couple of decades. Its innovations include EMIB (embedded multi-die interconnect bridge) and Foveros, technologies that allow multiple chips on a package to be connected side by side (EMIB) or stacked on top of one another in a 3D fashion (Foveros). The Disaggregated Manufacturing Organization (DMO) develops fab processes for Foveros base silicon interposer and Embedded multi-die interconnect silicon bride (EMIB) architectures to enable both internal and Foundry AP future roadmaps. The New Mexico DMO Technology Development Team is looking for a Product Integration engineer to join our EMIB/FOVEROS TD team. The EMIB/FOVEROS TD Product Integration team coordinates and drives the TD team's test vehicle/early product roadmap and schedules, by working with layout/design, tapeout, mask manufacturing, fab, and post fab teams to ensure EMIB/FOVEROS product requirements. Yield Analysis Engineer responsibilities include but are not limited to working with the fab team to define frame content to include on technology tape outs, layout reviews to ensure designs are DRC and correct sizing applied before mask manufacture, documenting product specific details, generating/auditing/improving New Product/Technology Introduction checklists, partnering with the TD team to ensure NPIs are intercepting expected process flow/recipes, coordinating and owning NPI scout lot setup/release/progress setting up flow, and developing strong partnerships with fab operations team to ensure critical NPI lots are meeting customer commitment. The ideal candidate should exhibit understanding of post fab/pre-shipping wafer requirements, knowledge of NPI Checklist systems, and the ability to prepare detailed, clear, and timely reports summarizing key lot status and driving organization to meet commitments. A basic understanding of the Interconnect process integration is a plus. Relocation assistance is provided.

Responsibilities

• Coordinate and drive the TD team's test vehicle/early product roadmap and schedules.
• Work with layout/design, tapeout, mask manufacturing, fab, and post fab teams to ensure EMIB/FOVEROS product requirements.
• Define frame content to include on technology tape outs with the fab team.
• Conduct layout reviews to ensure designs are DRC and correct sizing applied before mask manufacture.
• Document product specific details and generate/audit/improve New Product/Technology Introduction checklists.
• Partner with the TD team to ensure NPIs are intercepting expected process flow/recipes.
• Coordinate and own NPI scout lot setup/release/progress setting up flow.
• Develop strong partnerships with fab operations team to ensure critical NPI lots are meeting customer commitment.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Physics, Material Science and Engineering, Computer Science, Chemical Engineering, Mechanical Engineering, Chemistry, or related field.
• 1+ year(s) of experience with semiconductor processing fundamentals (lithography, wet and or dry etch, chemical and or mechanical polishing, etc.).
• 1+ year(s) of experience with materials characterization (SEM, TEM, etc.), materials fabrication, synthesis, or metrology.
• 6+ months experience with model-based problem-solving technique to solve complex problems.
• Statistical data analysis (JMP, Excel, MATLAB, etc.).
• Demonstrated STEM research experience.

Nice-to-haves

• Basic understanding of the Interconnect process integration is a plus.

Benefits

• Competitive pay
• Stock options
• Bonuses
• Health benefits
• Retirement plans
• Vacation time
• Relocation assistance
• Hybrid work model