Fellow Software Architect FPGA Static Timing Analysis

AMD - San Jose, CA

Full-time - Senior

San Jose, CA

Computer and Electronic Product Manufacturing

About the position

At AMD, we are on a mission to transform lives through technology, and we are looking for a Fellow Software Architect to lead the specification and development of FPGA Static Timing Analysis (STA) features for our next-generation STA tools. This role is pivotal in providing technical leadership and architectural guidance to enhance STA capabilities on both current and future devices, with a strong emphasis on performance, accuracy, and quality. As a Fellow Software Architect, you will be at the forefront of innovation, pushing the limits of what is possible in the realm of FPGA design and analysis. In this position, you will be responsible for designing, implementing, and testing FPGA STA capabilities that are essential for placement, optimization, routing, and signoff timing. You will conduct research and development of novel STA algorithms, as well as optimize existing algorithms to achieve significant improvements in quality of results (QOR), runtime, and memory usage, all while maintaining timing accuracy. Your role will also involve evaluating and providing STA support for new FPGA architectures, working closely with the field to resolve critical customer design issues, and collaborating with Tech Marketing and Applications Engineering to understand customer needs and drive the necessary STA support. We are looking for someone with a deep understanding of STA development who is ready to make an immediate impact by improving current software features and performance. You should be passionate about your work, self-motivated, detail-oriented, and capable of working both independently and collaboratively in a dynamic, fast-paced environment. Your insight into performance optimizations and ability to think of novel solutions will be crucial as you implement these ideas from concept to production. If you possess the drive, passion, and vision to build the software roadmap for STA capabilities, this is the role for you!

Responsibilities

• Designing, implementing, and testing FPGA STA capabilities suitable for placement, optimization, routing, and signoff timing.
• Conducting research and development of novel STA algorithms and optimizing existing STA algorithms to improve quality of results (QOR), runtime, and memory while maintaining timing accuracy.
• Evaluating and providing STA support for new FPGA architectures.
• Working with the field to close critical customer design issues.
• Collaborating with Tech Marketing and Applications Engineering to understand customer needs and drive required STA support.

Requirements

• Extensive experience in architecting and implementing high performance, high-capacity STA engines.
• Comprehensive understanding of multi-mode / multi-corner and variation aware STA.
• Experience working with multi-threaded / multi-process programs.
• Expertise in state-of-the-art EDA algorithms.
• Detailed knowledge of SDC timing constraints.
• Knowledge of Digital Design and FPGA implementation.
• Proficiency in C++ Programming.
• Solid foundation in software engineering, with strong analytical and debugging skills.
• Excellent verbal communication and writing skills, including executive level presentation skills.
• Experience with TCL, Python, Perl, or other scripting languages.
• Comfortable communicating with all levels of the organization, especially at the executive level.

Nice-to-haves

• Experience with FPGA design tools and methodologies.
• Familiarity with machine learning techniques applied to STA.
• Knowledge of hardware description languages (HDLs) such as VHDL or Verilog.

Benefits

• Base pay depending on skills, qualifications, experience, and location.
• Eligibility for annual bonuses or sales incentives.
• Opportunity to own shares of AMD stock through the Employee Stock Purchase Plan with discounts.
• Competitive benefits package.