FPGA/ASIC Validation, Staff Engineer

Full-time - Senior

Onsite - Sunnyvale, CA

Publishing Industries

About the position

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You are a highly skilled engineer with a passion for digital design and verification. You thrive in dynamic environments and are always eager to take on new challenges. Your attention to detail and analytical mindset allow you to tackle complex problems and deliver high-quality solutions. You have a strong foundation in FPGA design and are proficient in Verilog and SystemVerilog. You are well-versed in using various development tools and have experience in creating user documentation and test plans. You are a proactive team player who communicates effectively and collaborates seamlessly with cross-functional teams. Your technical prowess is complemented by your ability to understand and modify software drivers and scripts. You are committed to continuous learning and staying updated with the latest industry trends and technologies. Your previous experience in hardware development or verification positions you as a seasoned professional ready to make a significant impact at Synopsys.

Responsibilities

• RTL and FPGA design, implementation, and timing closure using Xilinx & Synopsys development tools.
• Verify the design in simulation using Verilog, SystemVerilog, and UVM (Universal Verification Methodology).
• Create user documentation.
• Create test plans for USB IP.
• Bring up and validate the design in the lab and generate test reports.
• Perform hardware validation tasks and debug IPs.
• Read, understand, and modify software drivers and scripts.

Requirements

• Experience in FPGA design.
• Proficiency in Verilog/SystemVerilog for RTL design and verification.
• Experience with Linux, C, C++, and scripting languages (Perl, Python, TCL) is highly desired.
• Familiarity with protocols such as AXI, USB, and PCIe is highly desired.
• Strong understanding of data structures and algorithms is highly desired.
• Experience using lab equipment, such as protocol analyzers, oscilloscopes, and logic analyzers.

Benefits

• Comprehensive health, wellness, and financial benefits.
• Annual bonus eligibility.
• Equity and other discretionary bonuses.