Next Step Systems - Phoenix, AZ

posted 17 days ago

Full-time - Mid Level
Onsite - Phoenix, AZ
Professional, Scientific, and Technical Services

About the position

The FPGA Design/Architect Engineer will lead the development of digital and firmware solutions, from architecture through to production ramp. This role requires expertise in designing and implementing digital circuits, particularly using Verilog or VHDL, and optimizing FPGA-based solutions for various applications. The engineer will collaborate with hardware and software teams to integrate FPGA designs into larger systems while staying updated on the latest technologies in embedded high-speed systems.

Responsibilities

  • Lead Digital and Firmware development from architecture, component selection, design, verification/validation to implementation and production ramp.
  • Design and implement digital circuits using Verilog or VHDL.
  • Develop and optimize FPGA-based solutions for specific applications.
  • Collaborate with hardware and software engineers to integrate FPGA designs into larger systems.
  • Stay up to date with the latest embedded high-speed systems technologies and industry trends.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field and 5+ years of experience.
  • Strong understanding of digital design fundamentals.
  • Proficiency in Verilog or VHDL.
  • Experience with FPGA development tools such as Xilinx, Altera, Vivado or Intel Quartus.
  • Knowledge of digital signal processing (DSP) and/or embedded systems is a plus.
  • Knowledge of new standards in Sensor Open Systems Architecture (SOSA).
  • Experienced with complex circuit board design process.
  • Excellent problem-solving and communication skills.
  • Ability to work effectively in a fast-paced environment and collaborate with cross-functional teams.

Nice-to-haves

  • Knowledge of digital signal processing (DSP) and/or embedded systems is a plus.
  • Knowledge of new standards in Sensor Open Systems Architecture (SOSA).
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