Graphics ASICS Hardware Design Engineer (San Diego/Santa Clara/Austin/Boxborough)

$151,000 - $227,000/Yr

Qualcomm - San Diego, CA

Full-time - Entry Level

San Diego, CA

Computer and Electronic Product Manufacturing

About the position

The Graphics ASICS Hardware Design Engineer at Qualcomm is responsible for micro-architecting and designing RTL for the Adreno GPU architecture, which is integral to Qualcomm's Snapdragon compute platforms. This role focuses on optimizing hardware design for performance, power, and cost, while also evaluating complex algorithms and requirements. The engineer will engage in verification, debugging, and troubleshooting throughout the project lifecycle, contributing to the development of cutting-edge graphics and compute technologies across various devices.

Responsibilities

• Micro-architect and design RTL for blocks and modules of Adreno GPU architecture.
• Identify advanced ways to optimize hardware design for better performance, power, and cost.
• Evaluate the hardware feasibilities of complex algorithms and requirements.
• Develop micro architecture and specification of the new generation design.
• Develop RTL for the corresponding micro architecture.
• Provide essential verification and debugging activities for the corresponding design throughout the entire project cycles.
• Optimize the silicon cost and improve clock speed.
• Troubleshoot silicon issues with products relevant to the corresponding design.

Requirements

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• Experience with Verilog/SystemVerilog design, Synopsys synthesis, low power design, test plan development, coverage-based design verification.
• Experience with Computer Architecture, Computer Arithmetic, Low power design, C/C++/Python programming languages.
• Experience in designing RTL for GPU, CPU, DSP, Machine-Learning, cache, controller, video, display, camera blocks in ASIC.

Nice-to-haves

• Exposure to Graphics API (OpenGL, Vulkan, Direct3D, etc) is a big plus.
• Good communication skills and desire to work as a team player.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants.
• Comprehensive benefits package designed to support success at work, at home, and at play.