Hardware Design Engineer 5 - Sr. Silicon Validation Eng.

$203,840 - $203,840/Yr

Protingent - Mountain View, CA

Full-time - Senior

Mountain View, CA

Administrative and Support Services

About the position

The Hardware Design Engineer 5 - Sr. Silicon Validation Engineer position at Protingent involves working within the Artificial Intelligence Silicon Engineering team to perform pre-silicon RTL verification, post-silicon validation, and systems-level testing. The role is focused on delivering high-quality designs for complex ASIC and FPGA systems, utilizing cutting-edge technology and methodologies. This contract position requires a highly motivated individual who thrives in a fast-paced environment and is capable of driving system team enablement and product deployment in data centers at scale.

Responsibilities

• Lead key components of functional validation of complex ASIC SOC and FPGA SOC.
• Perform Pre-Silicon SoC verification and Post-Silicon/FPGA validation by defining testing strategies.
• Work with cross-functional teams, including Architecture, Design, Verification, and Partner teams for project execution.
• Develop test plans, C tests, and infrastructure to complete functional validation of complex designs and report bugs/issues.
• Run tests, debug failures, and create stress and performance scenarios to meet test plan goals.
• Participate in chip bring-up and write test firmware to support various teams.
• Innovate to improve validation efficiency through methodologies and tools.
• Coach and mentor others in areas of expertise.

Requirements

• 10 years of experience with Design Verification work.
• 5 years of experience with UVM, Testbench development, and debugging.
• 5 years of experience with Test planning, Test writing, and Scripting.
• Bachelor's degree in computer science, electrical engineering, or a related field.
• Hands-on experience with UVM, Testbench Test case coding.
• Solid programming skills in C/C++, System Verilog, Assembly, and Python.
• Good knowledge of advanced computer architecture and boot flow.
• Experience with high-speed IOs and industry-standard bus/parallel/serial protocols like Ethernet, PCIE, JTAG, AXI, AHB, and I2C.

Nice-to-haves

• Hardware Debugging
• FPGA Timing/Speed Optimization
• Synopsys HAPS System
• C/C++
• AXI Bus
• Microprocessor Systems.

Benefits

• Competitive salaries
• Insurance plan options (HDHP plan or POS plan)
• Education/certification reimbursement
• Pre-tax commuter benefits
• Paid Time Off (PTO)
• Administered 401k plan